Grouped Scan Chain Clock Control for IC State Restoration
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Solution Overview
Problem
Integrated circuits face challenges in maintaining the integrity of scan chains during testing, particularly when different scan chains have varying lengths, as data in these chains can be overwritten, making seamless operation post-testing difficult.
Innovation Solution
Implementing a clock supply circuit with a detection mechanism that stops the clock signal to scan flip-flops once the desired bit sequence is fully loaded, ensuring that the scan chains maintain their pre-test state by preventing further data overwriting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is supplied to all scan chains during testing, then the testing process is simplified, but scan chains with different lengths cannot be properly restored to their pre-test state
Solution Approach 1:
The patent segments the scan chains into multiple groups based on their lengths, with each group receiving clock signals from a dedicated clock supply circuit. This segmentation allows different clock control strategies to be applied to different groups, enabling proper state restoration for scan chains of varying lengths while maintaining manageable circuit complexity.
Solution Approach 2:
The patent implements dynamic clock signal control where the clock supply circuit monitors the loading process and dynamically adjusts clock signal supply based on detection results. When a scan chain is fully loaded, the detection circuit signals the clock supply circuit to stop supplying clock signals to that specific chain, preventing data overwriting and ensuring proper state restoration.
2Productivity
If clock signals continue to be supplied after bit sequence loading is complete, then the testing process is simpler, but data in scan chains is overwritten and operation cannot continue
Solution Approach 1:
The patent implements a feedback mechanism where the detection circuit continuously monitors the loading status of scan chains and provides feedback signals to the clock supply circuit. When the detection circuit determines that a bit sequence has been completely loaded into a scan chain, it sends a feedback signal to stop the clock signal supply, thereby preventing further data overwriting and preserving data integrity.
Solution Approach 2:
The patent employs preliminary detection and control actions before data overwriting can occur. The detection circuit is set up to detect loading completion in advance, and the clock supply circuit is configured to suppress clock signals proactively once completion is detected, preventing the harmful effect of data overwriting before it happens.
3Reliability
If separate clock supply circuits are provided for each scan chain, then state restoration is achieved, but device complexity increases significantly
Solution Approach 1:
Instead of providing separate clock supply circuits for each individual scan chain, the patent segments scan chains into groups based on their lengths. Each group shares a common clock supply circuit, significantly reducing the total number of clock supply circuits needed while still enabling independent control of each scan chain within the group through the detection circuit feedback mechanism.
Solution Approach 2:
The patent makes clock supply circuits multi-functional by designing them to handle multiple scan chains within a group. Each clock supply circuit can selectively supply clock signals to different scan chains in its group based on detection feedback, allowing a single clock supply circuit to perform the function of multiple separate circuits would otherwise be needed.
Data Source
AI summary
In one example, an electronic device with an integrated circuit is provided. The integrated circuit includes a plurality of scan chains and a clock supply circuit for each group of one or more of the scan chains which have same length. The clock supply circuit is configured to supply a clock signal to the flip-flops of the group of scan chains. The clock supply circuit includes a detection circuit configured to detect, for at least one of the scan chains of the group, whether a bit sequence has been completely loaded into the scan chain. The clock supply circuit is configured to suppress the supply of the clock signal to the flip-flops of the group of scan chains in response to the detection circuit having detected that, for the at least one of the scan chains of the group, the bit sequence has been completely loaded into the scan chain.