Grouping Bit Interleaver Layout for Smaller Memory and Faster Access
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Solution Overview
Problem
Conventional block interleaving in digital communication systems results in inefficient memory usage, longer processing times, and larger address spaces, especially when using binary FEC decoders, due to the inefficient storage and access mechanisms.
Innovation Solution
The proposed solution involves a grouping bits interleaver design that stores and processes data bits in a register bank based on calculated bit positions, using a data storage unit and address and bit position calculator to optimize memory access and reduce memory size, incorporating a switch and bit-reversed-order operation circuit to manage data storage and retrieval efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional block interleaving is used, then burst errors can be spread into isolated bit errors, but memory size and address space increase significantly
Solution Approach 1:
The patent divides the memory storage into multiple groups, where each group stores a specific number of bits (e.g., 3 bits per group). This segmentation allows the interleaver to process and store data in smaller chunks, reducing the continuous memory address space requirement while maintaining the ability to spread burst errors across isolated positions through the grouping mechanism.
2Reliability
If conventional block interleaving is used, then burst errors can be spread into isolated bit errors, but processing time increases
Solution Approach 1:
The patent pre-calculates and stores the bit positions for each group in a lookup table during system initialization. During actual interleaving operations, the system simply retrieves pre-computed position information rather than calculating it in real-time, significantly reducing processing time while maintaining the error-spreading functionality of conventional block interleaving.
3Reliability
If conventional block interleaving is used, then burst errors can be spread into isolated bit errors, but memory usage efficiency decreases
Solution Approach 1:
The patent changes the fundamental parameter of how data is organized in memory by grouping bits into fixed-size units (e.g., 3 bits per group) and using non-contiguous address spacing. This parameter change allows multiple groups to share memory resources more efficiently, reducing overall memory usage while maintaining the error correction capability through proper distribution of grouped data across the memory structure.
Data Source
AI summary
An grouping bits interleaver includes a grouping bits unit and a data storage unit. The grouping bits unit is used for storing N data bits of an input data and outputting an address signal. Wherein each data bit is stored according to a bit position. The data storage unit coupled to the grouping bits unit is used for saving the content of the grouping bits according to the address signal. Compared to the conventional interleaver, the grouping bits interleaver has better memory usage, less access time, and smaller memory size.