Group-Wise LDPC Parity Interleaving for Fixed-Length Signaling

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Solution Overview

Problem

Current channel encoding and modulation techniques for signaling information in broadcast systems lack robustness and efficiency, necessitating the development of new methods optimized for signaling information transmission.

Innovation Solution

A parity interleaving apparatus and method that segment and group-wise interleave parity bits of an LDPC codeword, optimizing puncturing and interleaving based on specific sequences and code rates to enhance transmission efficiency for signaling information in broadcast systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional channel encoding and modulation techniques are used for signaling information transmission, then the system can maintain basic functionality, but the robustness and transmission efficiency are insufficient

Engineering Contradiction:

Improverobustness of signaling information transmissionVSAvoidtransmission efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The parity bits are divided into multiple groups (first parity bit group and second parity bit group) which are then independently interleaved using different interleaving orders. This segmentation allows different portions of the parity information to be distributed differently across the transmission medium, improving both robustness against burst errors and overall transmission efficiency

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different interleaving orders (first interleaving order and second interleaving order) to different parity bit groups. By changing the interleaving parameter for different segments of parity bits, the system achieves both enhanced robustness through diversified error distribution and improved transmission efficiency through optimized interleaving patterns

Inventive Principle:

Principle #35Parameter changes

2Reliability

If no parity interleaving is applied, then the encoding process is simpler and faster, but the error correction capability and transmission robustness are reduced

Engineering Contradiction:

Improveerror correction capabilityVSAvoidencoding process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The parity bits are segmented into multiple groups that can be independently processed. This segmentation enables the system to achieve improved error correction capability through group-wise interleaving while keeping the complexity manageable by processing each group separately rather than requiring complex full-block interleaving

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different interleaving orders are applied to different parity bit groups, providing enhanced error correction capability through parameter diversification. The use of multiple interleaving orders increases robustness while maintaining reasonable complexity by applying relatively simple interleaving operations to each group

Inventive Principle:

Principle #35Parameter changes

3Productivity

If all parity bits are transmitted without selective puncturing, then complete error correction information is available, but the transmission bandwidth utilization is reduced

Engineering Contradiction:

Improvebandwidth utilizationVSAvoiderror correction completeness

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The parity bits are divided into groups that can be selectively punctured. This segmentation enables the system to transmit only necessary parity information for certain code rates while maintaining complete error correction capability for other code rates, thereby improving bandwidth utilization without sacrificing reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements selective puncturing where only certain parity bit groups are transmitted based on the required code rate. This partial transmission of parity bits achieves efficient bandwidth utilization by avoiding transmission of redundant parity information while maintaining sufficient error correction capability through the interleaved structure of the transmitted portions

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11206047B2Parity interleaving apparatus for encoding fixed-length signaling information, and parity interleaving method using same

Publication Date: 2021.12.21 ELECTRONICS & TELECOMM RES INST

AI summary

A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.