GRPC Chip Testing with Request Sequencing for Multi-Chip Throughput
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Solution Overview
Problem
Existing chip test systems suffer from low efficiency, requiring long test times and high resource utilization due to limited one-to-one testing capabilities, which increases test costs and complexity.
Innovation Solution
A GRPC-based chip test method and apparatus that utilizes the GRPC protocol to enable simultaneous testing of multiple chips by sorting remote instrument call requests into an execution sequence, optimizing test resource utilization and reducing test time through distributed testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional one-to-one chip testing is used, then testing can be performed with simple equipment, but test efficiency is low and test time is long
Solution Approach 1:
The patent merges multiple chip testing operations into a single integrated system. The test instrument can simultaneously test multiple chips by receiving and processing multiple remote instrument call requests through GRPC protocol, combining what were previously separate one-to-one testing operations into a parallel multi-chip testing capability.
Solution Approach 2:
The test instrument is enhanced with multi-functionality to handle diverse testing scenarios. It can process different types of remote instrument call requests for multiple chips simultaneously, and the system supports both sequential and parallel testing modes, making the instrument adaptable to various testing requirements beyond simple one-to-one testing.
2Speed
If multiple chips are tested simultaneously, then test speed is improved, but resource utilization becomes more complex
Solution Approach 1:
The system implements dynamic resource management for simultaneous chip testing. The test instrument can dynamically allocate resources and adjust testing sequences based on chip priorities and test requirements. The GRPC-based request handling allows flexible dynamic scheduling of multiple testing operations, enabling the system to adapt resource allocation in real-time during the testing process.
Solution Approach 2:
The GRPC protocol acts as an intermediary layer between the test instrument and multiple chips. It standardizes communication and request handling, simplifying resource management by providing a unified interface for initiating and coordinating simultaneous testing operations across multiple chips, thereby reducing the complexity of direct multi-chip resource coordination.
3Reliability
If comprehensive chip testing is performed early, then chip competitiveness is improved, but test resource consumption increases
Solution Approach 1:
The testing system enables self-service capabilities where each chip can be independently tested through standardized GRPC requests. The test instrument autonomously manages the testing process for multiple chips without requiring extensive external coordination or additional physical resources for each chip, allowing comprehensive testing while optimizing resource utilization through automated request handling and parallel processing.
Data Source
AI summary
Embodiments of the present application provide a GRPC-based chip test method, a GRPC-based chip test apparatus, and a storage medium. The GRPC-based chip test method comprises: determining a number of to-be-tested chips that actually need to be tested among to-be-tested chips, and issuing a corresponding number of remote instrument call requests according to the number of to-be-tested chips that actually need to be tested; acquiring each of the remote instrument call requests based on a GRPC protocol; and sorting all the remote instrument call requests to form a request execution sequence table, and controlling the test instrument to sequentially test the to-be-tested chips that actually need to be tested according to the request execution sequence table.