Ground-Referenced Single-Ended Signaling for Chip Interconnects
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Solution Overview
Problem
Conventional chip-to-chip signaling techniques do not efficiently support multiprocessing performance targets in high-performance System-on-a-Chip (SoC) devices, leading to increased costs and compromised performance of feature-specific subsystems due to disparate fabrication process optimizations.
Innovation Solution
A ground-referenced single-ended signaling (GRS) system-on-package that includes interconnected chips with GRS interface circuits and electrical traces within a multi-chip module package, utilizing charge pump drivers and amplifiers to transmit pulses representing logic states, thereby improving bandwidth and immunity to noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing cores and subsystems are integrated onto a single SoC die, then high-performance may be achieved using conventional design techniques, but die cost can increase disproportionately with respect to die area
Solution Approach 1:
The patent divides the SoC system into multiple separate dies, each containing specific processing cores or subsystems. These segmented dies are then interconnected through a package-level interconnect structure, allowing functional integration without the cost penalties of a single large die. This segmentation enables cost-effective manufacturing while maintaining high system performance.
2Device complexity
If conventional chip-to-chip signaling techniques are used, then simpler signaling implementation is achieved, but multiprocessing performance targets are not efficiently supported
Solution Approach 1:
The patent transitions from conventional two-dimensional planar signaling to a three-dimensional vertical signaling architecture. Multiple signaling layers are stacked vertically within the package, enabling high-bandwidth communication between dies without increasing the horizontal footprint. This dimensional change supports multiprocessing performance targets while maintaining manageable signaling complexity.
3Productivity
If a die fabrication process optimized for CPU core is selected, then CPU core performance is maximized, but performance of feature-specific subsystems may be compromised
Solution Approach 1:
The patent applies different fabrication process optimizations to different dies based on their specific functional requirements. CPU cores are fabricated using processes optimized for digital logic performance, while feature-specific subsystems use processes tailored to their particular needs. This local quality approach ensures each subsystem operates at peak performance without compromising others.
Data Source
AI summary
A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.