Ground-Referenced Single-Ended Interconnect for Multi-Chip Modules
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Solution Overview
Problem
Conventional computing systems face challenges in achieving high performance and integration due to increasing manufacturing costs associated with integrating multiple processing cores onto a single chip, and conventional chip-to-chip signaling techniques do not efficiently support multiprocessing performance targets.
Innovation Solution
A system of interconnected chips using a multi-chip module (MCM) with ground-referenced single-ended signaling (GRS) interfaces and interconnects, which includes a GRS data driver and receiver configuration to enable high-speed, single-ended signaling between chips, reducing manufacturing costs and improving bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing cores are integrated onto a single chip to achieve higher performance and integration, then processing capability is improved, but manufacturing cost increases disproportionately with die area
Solution Approach 1:
The patent divides the multi-core processor into multiple separate chips, each containing one or more processing cores. These discrete chips are then interconnected through a package-level interconnect architecture, allowing independent fabrication and assembly while achieving multi-core functionality. This segmentation resolves the cost issue by avoiding the exponential cost increase associated with large single-die areas.
Solution Approach 2:
The patent implements a hierarchical structure where multiple processor chips are nested within a common package substrate. The interconnect circuitry is embedded within the package layers, creating a nested architecture where chips, interconnects, and packaging elements are integrated at different hierarchical levels. This allows cost-effective multi-core implementation without requiring a single large die.
2Productivity
If multiple processing cores are integrated onto a single chip to achieve higher performance, then processing capability is improved, but signaling efficiency between cores deteriorates
Solution Approach 1:
The patent introduces a package-level interconnect circuit as an intermediary between processor chips. This interconnect architecture provides dedicated high-speed signaling paths that are optimized for multi-core communication, resolving the signaling efficiency deterioration that would occur with conventional chip-to-chip interfaces. The interconnect acts as a mediator that enables fast communication between segregated cores.
3Device complexity
If conventional chip-to-chip signaling techniques are used to connect multiple chips, then device complexity is reduced, but bandwidth and performance between chips deteriorate
Solution Approach 1:
The patent changes the electrical parameters of the interconnect system by implementing controlled impedance signaling with specific voltage levels and signal timing characteristics optimized for high-speed operation. The interconnect uses differential signaling with controlled impedance traces, and employs signal equalization techniques to maintain signal integrity over the package interconnect distance. These parameter changes enable high bandwidth while managing the complexity through standardized interface protocols.
Data Source
AI summary
A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.