Ground-Referenced Single-Ended Signaling for Multi-Chip Module Interconnects
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Solution Overview
Problem
The increasing complexity and integration of graphics processing unit (GPU) chips lead to disproportionate manufacturing costs due to larger die areas, resulting in cost inefficiencies and a need for improved GPU architecture.
Innovation Solution
A multi-chip module (MCM) system with ground-referenced single-ended signaling (GRS) that connects multiple processor and graphics processing cluster (GPC) chips through a common package, utilizing charge pump drivers and amplifiers to enable high-speed, noise-immune communication, reducing the need for increased die area and associated costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more GPC partitions and FB partitions are integrated onto a single GPU chip to achieve higher performance, then system performance is improved, but manufacturing cost increases disproportionately due to larger die area
Solution Approach 1:
The patent divides the GPU system into multiple separate chips (GPC chip, FB chip,, and processor chip) packaged together in an MCM module. This segmentation allows each chip to be manufactured at optimal die sizes, avoiding the exponential cost increase associated with fabricating all components on a single large die while maintaining high system performance through integrated packaging.
2Reliability
If differential signaling is used to achieve noise immunity, then communication reliability is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent introduces ground-referenced single-ended signaling as an intermediary communication method between chips. This approach uses a common ground reference plane in the MCM package to provide noise immunity similar to differential signaling, but with simpler circuit implementation and lower power consumption by eliminating the need for paired differential signal lines.
3Quantity of substance
If higher circuit density is achieved through fabrication technology advances, then more partitions can be integrated, but die area costs continue to increase
Solution Approach 1:
The patent transitions from integrating all circuits on a single two-dimensional die to a three-dimensional MCM architecture where multiple chips are vertically stacked and interconnected within a common package. This dimensional change allows high circuit density to be achieved through vertical integration rather than horizontal expansion, avoiding the disproportionate cost increase associated with larger die areas.
Data Source
AI summary
A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.