Gate-Turn-Off Thyristor Segmented Emitter Design
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Solution Overview
Problem
Gate-turn-off thyristors face limitations in resistance to dI/dt and dV/dt, requiring complex circuits and are only suitable for high current and voltage applications, with a narrow range of 1000 A or more and 2500 V or more, and have large die sizes that restrict their application.
Innovation Solution
A gate-turn-off thyristor design featuring a plurality of N-type emitter regions with high doping concentration on a silicon substrate, surrounded by P-type dense base regions, with a cathode metal layer on the emitter regions and a thin P-type emitter region of the lower transistor, along with a manufacturing method that includes specific masking and processing steps to reduce silicon wafer thickness and enhance current and voltage handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the cell size is large (prior art), then the manufacturing process is simpler, but the peripheral current density is too high which limits dI/dt and dV/dt resistance
Solution Approach 1:
The emitter region is divided into multiple discrete emitter fingers or emitter cells arranged in parallel. This segmentation increases the total peripheral length of the emitter region without increasing the overall device area, thereby reducing the current density at each peripheral point while maintaining manufacturing simplicity through modular structure replication.
2Reliability
If the cell density is increased to reduce peripheral current density, then the dI/dt and dV/dt resistance is enhanced, but the device complexity increases
Solution Approach 1:
Adjacent emitter cells share common base regions and contact structures. This merging approach allows increasing cell density and peripheral length while reducing the number of discrete components and interconnections needed, thereby enhancing dI/dt and dV/dt resistance without proportionally increasing device complexity.
3Power
If the gate-turn-off thyristor is designed for high current applications (1000 A or more), then the device can handle high power, but it is not suitable for medium current applications (50-500 A)
Solution Approach 1:
The device incorporates adjustable parameters such as gate resistance, emitter area, and cell configuration that can be optimized for different current ranges. This dynamic design allows the same thyristor structure to be adapted for medium current applications (50-500 A) while maintaining the capability for high current applications through parameter adjustment rather than requiring completely different device designs.
4Quantity of substance
If the die size is large, then the current handling capability is high, but the chip production cost increases and efficiency decreases
Solution Approach 1:
The large current handling capability is achieved through multiple parallel emitter cells rather than a single large emitter. This segmentation allows the device to maintain high current capability while using a smaller overall die area, enabling higher chip production efficiency and lower costs while still handling high currents through the combined capacity of multiple smaller emitter units.
Data Source
AI summary
A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor.