Guard Region Biasing for Through-Silicon Via Parasitic Diode Suppression
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Solution Overview
Problem
Conventional semiconductor integrated circuits with through silicon vias (TSVs) face issues of increased resistance and bias voltage fluctuations due to the formation of parasitic diodes, leading to current path formation, signal transmission delays, noise, and potential latch-up phenomena, which increase production time and cost.
Innovation Solution
Incorporating a guard region around the TSVs with a different impurity concentration to apply a compensatory bias voltage, preventing the formation of a current path and maintaining a backward bias across the metal-semiconductor junction, thereby reducing resistance and stabilizing bias voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through silicon via is formed to penetrate the semiconductor chip, then electrical connection between stacked chips is achieved, but resistance increases and bias voltage becomes unstable due to parasitic diode formation
Solution Approach 1:
An insulation layer is introduced as an intermediary between the through silicon via and the semiconductor chip substrate. This insulation layer prevents direct contact between the metal via and the silicon substrate, thereby eliminating parasitic diode formation while maintaining electrical connection functionality between stacked chips
Solution Approach 2:
The electrical properties of the interface between the through silicon via and the semiconductor chip are changed by introducing an insulation layer with different electrical characteristics. This parameter change prevents charge carrier injection and eliminates the parasitic diode effect, stabilizing bias voltage
2Area of stationary object
If the semiconductor chip area is reduced to meet miniaturization demands, then packaging density improves, but resistance increases due to smaller cross-sectional area
Solution Approach 1:
The semiconductor chip is designed with non-uniform impurity distribution, creating regions of different electrical properties. High-concentration impurity regions are positioned near the through silicon via to locally reduce resistance, while other regions maintain smaller area for miniaturization. This local quality variation allows area reduction without proportionally increasing resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents current path formation, minimizes semiconductor chip failures, reduces production time and cost, and enhances the reliability and stability of semiconductor integrated circuits.
Implementation Method 1
a through-chip-via arranged to penetrate the well and electrically connected to the first and second external electrodes
Implementation Method 2
a guard region disposed around the through-chip-via with space in-between and arranged to apply a second well bias voltage to the well... maintaining a backward bias across the metal-semiconductor junction
Data Source
AI summary
A semiconductor integrated circuit includes a semiconductor chip. The semiconductor chip includes a well arranged to receive a first well bias voltage from a well biasing region, a through-chip-via arranged to penetrate the well, and a guard region disposed around the through-chip-via with space in-between and arranged to apply a second well bias voltage to the well.