Semiconductor Guard Ring Layout for BPG Portability
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Solution Overview
Problem
Current semiconductor design rules struggle to accommodate variability between non-buried and buried power grid architectures, requiring adaptive redesigns to ensure compliance with specific power grid types, which complicates the manufacturing and porting of semiconductor devices.
Innovation Solution
A dual-architecture-compatible layout diagram is generated, featuring both non-buried and buried power grid structures, allowing for selective pruning to adapt to either architecture without needing adaptive redesign, by configuring guard rings and power grids to accommodate different reference voltages and routing configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design rules are specific to a single power grid architecture (non-BPG or BPG), then compliance with that architecture is ensured, but adaptive redesign is required when switching between architectures, increasing device complexity and manufacturing time
Solution Approach 1:
The patent creates a universal layout diagram that can represent both non-BPG and BPG power grid architectures through selective pruning. The parent layout diagram includes all necessary elements for both architectures, allowing it to serve multiple functions. By selectively removing (pruning) specific elements, the same parent diagram can be adapted to either architecture type without requiring complete redesign, thus resolving the contradiction between ensuring compliance and avoiding adaptive redesign complexity
Solution Approach 2:
The patent performs preliminary action by pre-configuring the parent layout diagram with all possible power grid elements (both non-BPG and BPG structures) before the final architecture is selected. This preliminary inclusion of all potential elements allows for easy adaptation later through simple pruning operations, rather than requiring complex redesign when switching between architectures
2Manufacturing precision
If design rules are specific to a single power grid architecture, then manufacturing precision for that architecture is improved, but porting between architectures requires extensive redesign, increasing loss of time
Solution Approach 1:
The parent layout diagram is prepared in advance with all necessary elements for both non-BPG and BPG architectures already included. This preliminary configuration allows rapid porting between architectures through selective pruning rather than extensive redesign, significantly reducing the time loss when switching between power grid types while maintaining manufacturing precision for the target architecture
Solution Approach 2:
The patent segments the power grid elements into distinct, independently prunable components. By organizing the layout diagram with separable non-BPG and BPG elements, the system enables selective removal of unnecessary segments based on the target architecture, allowing quick adaptation without affecting the remaining compliant elements and minimizing redesign time
3Reliability
If guard rings and power grids are configured for a specific architecture, then electrical performance is optimized, but flexibility to accommodate different reference voltages and routing configurations is reduced
Solution Approach 1:
The parent layout diagram is designed with universal guard ring and power grid configurations that can accommodate both non-BPG and BPG architectures. The same parent structure supports different reference voltages and routing configurations by selectively enabling or disabling specific elements through pruning, thus maintaining electrical performance optimization for the target architecture while preserving flexibility to adapt to different architectural requirements
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first protected circuit; a first guard ring; and a second guard ring adjacent to the first guard ring and around the first protected circuit. The second guard ring includes a first via tower configured to provide a first reference voltage; a second via tower configured to provide a second reference voltage different than the first reference voltage; and at least a third via tower configured to provide the first reference voltage.