Semiconductor Guard Ring Crack Detection via Insulated Interconnects
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Solution Overview
Problem
Current semiconductor devices face challenges in detecting cracks or peelings during the dicing process, leading to defects and yield degradation, as conventional methods like visual inspection are inadequate for identifying micro-cracks and can't differentiate between internal and external issues, and dedicated crack detection circuits increase chip size and complexity.
Innovation Solution
Incorporating an existing circuit in the semiconductor device as a crack detector, with a crack detection line arranged on the guard ring or beneath electrode pads, using an insulating layer to prevent electrical coupling, allowing for detection of cracks or peelings without increasing chip size or requiring additional components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If visual inspection is used to detect cracks, then the inspection process is simple, but micro-cracks cannot be detected and internal/external issues cannot be differentiated
Solution Approach 1:
The patent reuses existing functional circuits (I/O circuits, voltage generator circuits, or crack stopper circuits) that are already present in the semiconductor device to perform crack detection. By making these existing circuits serve dual purposes - their original function plus crack detection - the system achieves high measurement precision without adding dedicated detection components, thus avoiding increased device complexity
Solution Approach 2:
The semiconductor device performs self-diagnosis by using its own internal circuits to detect cracks. The I/O circuits, voltage generator circuits, or crack stopper circuits monitor their own operational status and detect cracks through changes in their electrical characteristics, eliminating the need for external inspection equipment
2Reliability
If dedicated crack detection circuits are added, then crack detection capability is improved, but chip size and device complexity increase
Solution Approach 1:
The patent makes existing circuits perform dual functions - their original purpose plus crack detection. For example, I/O circuits that normally handle data input/output are also used to detect cracks by monitoring for breaks or short circuits. This eliminates the need for separate dedicated detection circuits, maintaining small chip size while achieving reliable crack detection capability
Solution Approach 2:
The patent combines the crack detection function with existing functional circuits by placing detection lines in the same interconnect layers or using the same circuit paths. This merging of functions into existing structures avoids adding separate detection components that would increase chip area
3Area of stationary object
If existing circuits are used for crack detection, then chip size is maintained, but electrical coupling must be prevented between detection lines and functional circuits
Solution Approach 1:
The patent introduces insulating layers as intermediary structures between detection lines and functional circuits. These insulating layers act as mediators that prevent unwanted electrical coupling while allowing the detection lines to be routed through the same interconnect layers as functional circuits, thus maintaining compact chip size without creating electrical interference
Solution Approach 2:
The patent applies insulation selectively only where needed - specifically at locations where detection lines pass through or near functional circuits. Rather than insulating entire regions, the insulating layers are placed locally at critical coupling points, minimizing the impact on chip area while effectively preventing electrical interference
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor substrate including an element region, a guard ring provided on an outer periphery of the element region and including a first interconnect and a first plug which electrically couples the first-interconnect and a first well region, a second interconnect provided above the first interconnect via a first insulating layer and non-electrically coupling to the first interconnect, and a first circuit coupled to the second interconnect. The first circuit detects one of a crack and a peeling of the guard ring in accordance with a break in the second interconnect or a short circuit between the second interconnect and the first interconnect.