Guard Ring Structure for Reducing Leak Current in Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices with p-type guard rings suffer from leak current issues due to the wide electric field distribution in the outermost guard ring, leading to reduced withstand voltage, as crystal defects in high concentration regions cause electric field leakage.
Innovation Solution
The semiconductor device design includes p-type guard rings with a high concentration region and a low concentration region, where the low concentration region on the outermost guard ring has a wider width, reducing the electric field application to the high concentration region and minimizing leak current, while narrowing the second parts between high concentration regions to enhance withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the outermost guard ring has a high concentration region with wide electric field distribution, then the guard ring can effectively surround the element region, but leak current occurs due to crystal defects in the high concentration region
Solution Approach 1:
The patent applies local quality by creating different concentration regions within the guard ring structure. The outermost guard ring includes a low concentration region at its outer peripheral end, while inner guard rings maintain high concentration regions throughout. This localized variation in impurity concentration allows the outermost guard ring to have reduced electric field application at the problematic outer peripheral end, thereby suppressing leak current caused by crystal defects, while other regions maintain their protective function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively restrains leak current and improves the withstand voltage of the semiconductor device by controlling the electric field distribution and reducing crystal defect exposure, thereby enhancing device performance.
Implementation Method 1
an electric field is generated in a pn junction 100a (a boundary surface between the guard ring 100 and the outer-periphery drift region 110) positioned at an outer peripheral end of the guard ring 100. A width Wa1 of a distribution range of the electric field in an outermost guard ring 100x, which is a guard ring placed on outermost peripheral side, is wider than widths Wb1 of respective distribution ranges of the electric field in the other guard rings 100.
Implementation Method 2
In each guard ring 100, a p-type impurity concentration is distributed such that the p-type impurity concentration is high at a central part and decreases toward a peripheral part (a part near an outer-periphery drift region 110).
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, which includes an element region and an outer-periphery voltage withstanding region. The outer-periphery voltage withstanding region includes a plurality of p-type guard rings surrounding the element region in a multiple manner. Each of the guard rings includes a high concentration region and a low concentration region. A low concentration region of an outermost guard ring includes a first part positioned on an outer peripheral side of its high concentration region. Respective low concentration regions of the guard rings include respective second parts, each positioned in a range sandwiched between corresponding two adjacent high concentration regions among a plurality of concentration regions. A width of the first part on a front surface is wider than widths of the second parts on the front surface.