Guard Ring Isolation Structure for Power Device Noise Blocking
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Solution Overview
Problem
High-voltage power devices in semiconductor chips generate noise that can interfere with adjacent low-voltage CMOS devices, leading to issues like latch-up and parasitic current, which existing guard ring structures fail to adequately address.
Innovation Solution
A semiconductor device with a guard ring structure comprising multiple guard rings of alternating conductivity types, surrounded by a deep well region, which receive the same bias voltage and are connected to the power supply, effectively blocking noise by capturing drifting hole carriers and suppressing parasitic transistor operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-voltage power device is embedded within a power management integrated circuit, then the device can be manufactured together with various circuits in a semiconductor chip, but noise problems occur with adjacent low-voltage CMOS devices
Solution Approach 1:
The semiconductor chip is divided into distinct regions: a power block containing the high-voltage power device and a separate circuit block containing low-voltage CMOS devices. The guard ring structure creates an intermediate zone between these blocks, physically segmenting the chip to prevent noise propagation from the power device to the CMOS devices while maintaining integration.
2Object-affected harmful factors
If a guard ring structure is provided to remove noise generated from the power device, then noise interference is reduced, but the structure complexity increases
Solution Approach 1:
The guard ring structure employs nested concentric rings with alternating conductivity types (N-type and P-type) arranged in layers. The first guard ring of N-type surrounds the power device, the second guard ring of P-type surrounds the first guard ring, and the third guard ring of N-type surrounds the second guard ring. This nested configuration efficiently captures drifting hole carriers through multiple layers while maintaining a compact footprint and systematic structure.
3Reliability
If multiple guard rings of alternating conductivity types are used to capture drifting hole carriers, then parasitic current is suppressed, but the manufacturing process becomes more complex
Solution Approach 1:
The guard ring structure follows a periodic pattern of alternating N-type and P-type conductivity layers arranged concentrically. This periodic alternation of conductivity types creates a systematic structure that efficiently captures drifting hole carriers at each interface while maintaining regular, repeatable manufacturing steps. The periodic arrangement allows for standardized fabrication processes compared to irregular or random doping patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed guard ring structure effectively suppresses noise and parasitic current, reducing interference between high-voltage and low-voltage devices, thereby enhancing the reliability and stability of semiconductor chips.
Implementation Method 1
effectively blocking noise by capturing drifting hole carriers
Implementation Method 2
suppressing parasitic transistor operations
Data Source
AI summary
A power device and a guard ring structure surrounding the power device are provided. The power device includes: a buried layer of a first conductivity type and a buried layer of a second conductivity type disposed within a substrate; a body region of the first conductivity type and a drift region of the second conductivity type disposed on the buried layer of the first conductivity type; and a gate electrode, a source electrode, and a drain electrode disposed on the body region of the first conductivity type and the drift region of the second conductivity type. The guard ring structure includes: a first guard ring of the second conductivity type adjacent to the power device; a second guard ring of the first conductivity type adjacent to the first guard ring; and a third guard ring of the second conductivity type adjacent to the second guard ring.