3D Guard Ring Structure for Sawing Stress in Semiconductor Chips
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Solution Overview
Problem
The sawing process in semiconductor manufacturing generates stress that can cause defects such as cracks in material layers of integrated circuits due to the transfer of stress during the cutting of semiconductor chips, which existing guard rings fail to adequately address.
Innovation Solution
A guard ring design featuring conductive patterns and plugs with specific orientations and connections, including long and short patterns, that support internal insulating layers by connecting them to external layers through open portions in the long patterns, thereby preventing the collapse and isolation of these layers during the sawing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional guard ring structure is used, then the chip region is surrounded for basic protection, but the insulating layers collapse and isolate during the sawing process due to stress transfer
Solution Approach 1:
The conductive plug is segmented into multiple conductive patterns (first conductive pattern, second conductive pattern, third conductive pattern) stacked in the vertical direction. These segmented conductive patterns are spaced apart from each other, creating a multi-level support structure that effectively distributes and manages stress during the sawing process, preventing insulating layer collapse.
Solution Approach 2:
The solution transitions from a conventional planar guard ring to a three-dimensional structure by stacking multiple conductive patterns vertically. The conductive patterns are arranged at different heights (first direction perpendicular to substrate) with spacing between them, creating a vertical dimension that provides enhanced mechanical support and stress distribution throughout the insulating layers.
2Ease of manufacture
If the guard ring structure is simplified, then manufacturing is easier, but the ability to prevent stress transfer and maintain insulating layer integrity deteriorates
Solution Approach 1:
The conductive plug is divided into multiple discrete conductive patterns stacked vertically with spacing between them. This segmentation allows each pattern to be formed using standard photolithography and deposition processes, maintaining ease of manufacture while the multi-level structure provides enhanced stress distribution and insulating layer support compared to a single-layer design.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; and a guard ring including a plurality of conductive patterns stacked over the semiconductor substrate in a first direction to be spaced apart from each other, and a conductive plug disposed between two adjacent conductive patterns among the plurality of conductive patterns, the first direction being perpendicular to a top surface of the semiconductor substrate, wherein the conductive plug includes a plurality of long patterns and a plurality of short patterns.