Guard Ring Stress Reduction via Silicon Material Switch
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Solution Overview
Problem
Integrated circuits with embedded silicon-germanium (eSiGe) strain engineering technology are vulnerable to stress defects at corners of larger eSiGe structures, such as guard rings, leading to potential functional failures due to concentrated mechanical stress and lattice defects.
Innovation Solution
Forming guard ring structures from single-crystal silicon instead of eSiGe, which reduces the vulnerability to stress-induced defects while maintaining the benefits of eSiGe source/drain regions for enhanced carrier mobility in transistors, by using a mask layer to protect guard ring regions during recess etch and selective epitaxy processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If guard ring structures are formed from embedded silicon-germanium (eSiGe) to maintain consistency with source/drain regions, then manufacturing process simplicity is improved, but stress-induced lattice defects and junction failures occur at corners of larger eSiGe structures
Solution Approach 1:
The patent applies different materials to different regions: eSiGe is used for source/drain regions where stress enhancement is beneficial, while single-crystal silicon is used for guard ring structures where stress concentration would cause defects. This local differentiation resolves the contradiction by optimizing each region's material properties for its specific function.
Solution Approach 2:
The manufacturing process is segmented into separate steps: forming single-crystal silicon guard rings first, then selectively forming eSiGe source/drain regions in non-guard ring areas. This segmentation allows each structure type to be optimized independently, preventing stress defects while maintaining manufacturing feasibility.
2Stability of the object's composition
If eSiGe is used in all regions including guard rings, then material consistency is improved, but carrier mobility enhancement is lost in guard ring regions and stress defects occur
Solution Approach 1:
Different material compositions are applied to different functional regions: eSiGe for transistor source/drain regions requiring carrier mobility enhancement, and single-crystal silicon for guard rings where stress-free operation is critical. This resolves the contradiction by prioritizing functional requirements over material uniformity.
3Ease of operation
If larger eSiGe structures with corners are formed, then guard ring functionality is maintained, but mechanical stress concentrates at corners causing lattice defects
Solution Approach 1:
The material parameter (crystal structure) is changed from eSiGe to single-crystal silicon for guard ring structures. This parameter change eliminates the lattice mismatch and stress concentration issues inherent in eSiGe, particularly at corner regions, while preserving the guard ring's electrical isolation functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes lattice defects and prevents junction failures, ensuring reliable integrated circuit performance without degrading carrier mobility enhancements in transistors, and does so without requiring additional chip area or compromising guard ring functionality.
Implementation Method 1
a mask layer is applied to regions of the surface of the semiconducting body at which the active transistors are being formed, to prevent recess etch of guard ring structures
Implementation Method 2
The exposed locations are filled with selective epitaxy of a silicon-germanium alloy
Implementation Method 3
the guard ring structures and source/drain regions receive ion implantation of a dopant species
Data Source
AI summary
An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated.