Guard Ring Through Via Structure for Thermal Stress Relief
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Solution Overview
Problem
Existing through vias in semiconductor integrated circuits experience stress and reliability issues due to mismatched thermal expansion coefficients, leading to structural degradation and delamination at interfaces, particularly at the BEOL and device substrate junctions.
Innovation Solution
A TSV design with specific dimensions and ratios of length and width, along with a guard ring, is implemented to minimize stress and improve etching process control, reducing stress concentration at interfaces and enhancing structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing through vias are used to connect stacked ICs, then electrical and physical connections are achieved, but stress and reliability issues occur due to mismatched thermal expansion coefficients
Solution Approach 1:
The patent employs a composite via structure consisting of a first via material and a second via material with different thermal expansion coefficients. The first via material (e.g., copper) provides excellent electrical conductivity, while the second via material (e.g., tungsten or cobalt) has a thermal expansion coefficient better matched to the surrounding semiconductor materials. This composite approach allows the via structure to accommodate thermal stress differentials, preventing delamination and structural degradation while maintaining reliable electrical connections.
2Productivity
If through vias are implemented in stacked IC packages, then functional density is increased, but stress concentration and delamination occur at interfaces
Solution Approach 1:
The patent applies local quality by creating a via structure with spatially varying material properties. The first via material is positioned in a first portion of the via, while the second via material is positioned in a second portion, allowing each material to be optimized for its specific location's requirements. This local differentiation enables the via to handle stress concentrations at critical interfaces while maintaining overall structural integrity and enabling high functional density in stacked packages.
3Ease of manufacture
If conventional via structures are used, then manufacturing process is simple, but etching process control and stress distribution are poor
Solution Approach 1:
The patent implements preliminary action by forming the first via material before forming the second via material. This sequential approach allows the first via material to be deposited and partially processed, then the second via material is added to complete the via structure. This preliminary staging enables better control over etching processes and stress distribution, as each material layer can be optimized independently while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed TSV design optimizes stress distribution and improves reliability by balancing stress concentrations, enhancing the structural integrity and reducing etching-induced defects, thereby improving the overall performance and reliability of semiconductor structures.
Implementation Method 1
Existing through vias in semiconductor integrated circuits experience stress and reliability issues due to mismatched thermal expansion coefficients
Data Source
AI summary
An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.