Guard Ring TSV Structure for Interface Stress Relief
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Solution Overview
Problem
Existing through vias in IC packaging technologies generate stress at the interface region between the device substrate and the BEOL structure, particularly due to differences in thermal expansion coefficients and insertion depth, which can lead to reliability issues such as cracking and delamination.
Innovation Solution
The proposed solution involves a specific design for the through substrate via (TSV) with tailored dimensions, where the TSV extends along a first direction through a substrate, with a total length composed of two portions: one in the BEOL structure and one in the device substrate. The ratio of the first length to the second length is optimized between 0.25 to 0.5 to minimize stress, and the width of the TSV is optimized relative to its length to enhance etching process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TSV extends deeply into the device substrate to improve electrical connection, then the electrical connectivity is enhanced, but the stress concentration at the interface region increases leading to cracking and delamination
Solution Approach 1:
The patent applies parameter changes by optimizing the ratio of the first length (in BEOL structure) to the second length (in device substrate) of the TSV to be between 0.25 to 0.5. This specific parameter range reduces stress concentration at the interface region while maintaining adequate electrical connectivity, resolving the contradiction between deep extension for connectivity and stress reduction for reliability
Solution Approach 2:
The patent implements local quality by creating a guard ring structure made of stress-compensating material positioned around the TSV at the interface region. This local structural modification addresses the stress concentration problem specifically at the critical interface area without affecting the overall TSV functionality or electrical connection quality
2Object-affected harmful factors
If the TSV dimensions are increased to reduce stress, then the stress distribution is improved, but the etching process control becomes more difficult
Solution Approach 1:
The patent resolves this contradiction by establishing specific parameter ranges: the width-to-length ratio of the TSV is optimized, and the length ratio between the two portions is set between 0.25 to 0.5. These parameter specifications achieve improved stress distribution while remaining within manufacturable dimensions that maintain etching process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces stress at the interface region, improves stress distribution, and enhances the reliability of the TSV by minimizing the impact of thermal stresses and mechanical stresses, thereby reducing the likelihood of cracking and delamination.
Implementation Method 1
differences in thermal expansion coefficients and insertion depth, which can lead to reliability issues such as cracking and delamination
Data Source
AI summary
An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.