Guarded Electrical Overstress Protection Circuit With Low Leakage
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Solution Overview
Problem
Conventional electrical overstress protection circuitry for low-level input pins in monolithic mixed-signal semiconductor products allows reverse leakage currents, which exceed specifications and degrade circuit performance, and lacks effective on-chip testing capabilities.
Innovation Solution
The implementation of a guarded electrical overstress protection circuit with an intermediate node receiving a reference voltage and pairs of clamp devices of opposite polarity, clamping the input signal line to the intermediate node and to reference potentials, reduces reverse leakage currents while providing protection against overstress events, and enables on-chip testing by maintaining a guard node at the same potential as the input pin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clamp circuits are used to provide EOS protection, then protection against electrical overstress is achieved, but reverse leakage currents exceed specifications and degrade circuit performance
Solution Approach 1:
The clamp circuit is segmented into two independent parts: a first clamp device connecting the input signal line to a first reference potential, and a second clamp device connecting the input signal line to a second reference potential. Each clamp device is independently controlled by its own control signal, allowing separate optimization of their operating characteristics to minimize leakage currents while maintaining EOS protection.
Solution Approach 2:
The clamp devices transition from static to dynamic operation by using control signals to adjust their clamping characteristics in real-time. The control signals are generated based on the operational state of the circuit, enabling the clamp devices to adapt their leakage current characteristics dynamically - operating in a high-impedance state during normal operation to minimize leakage, and activating only during EOS events.
2Reliability
If clamp devices are continuously active to provide protection, then EOS protection is maintained, but leakage currents increase and noise is introduced on the input signal line
Solution Approach 1:
The clamp devices operate periodically rather than continuously, being activated only when EOS events are detected. The control signals enable the clamp devices to switch between active and inactive states based on operational conditions, providing protection during critical periods while remaining inactive during normal operation to avoid introducing noise and leakage currents.
3Adaptability or versatility
If test signal pin is connected to input signal line through multiplexer, then on-chip testing capability is provided, but additional leakage paths are introduced and circuit performance is degraded
Solution Approach 1:
An intermediate buffer stage is introduced between the test signal pin and the input signal line. This buffer acts as an intermediary that isolates the test path from the signal path, preventing direct leakage current paths while still enabling test signal injection. The buffer's high input impedance and low output impedance characteristics allow it to couple test signals effectively while blocking leakage currents from affecting the main circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution minimizes noise on the input signal line, reduces leakage currents to less than picoampere levels, and allows for effective overstress protection and on-chip testing without degrading normal operation, enhancing the compatibility with low-leakage systems like digital X-ray medical imaging.
Implementation Method 1
a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials
Data Source
AI summary
Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.