Guarded Memory Access for Multi-Thread Safe SYSTEMC Simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SYSTEMC simulations face challenges in achieving reproducibility and multi-thread safety, especially when executed on multi-core processors, due to data races and the need for synchronization that affects performance compliance with IEEE Std. 1666-2011 standards.
Innovation Solution
Implementing multi-thread safe system level modeling simulation (SLMS) through deferred execution, direct memory interface (DMI) access in exclusive execution mode, and guarded memory access to ensure reproducibility and prevent data races by scheduling operations that access shared resources sequentially and controlling memory access to prevent concurrent modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-threading is used to speed up SYSTEMC simulation, then simulation speed is improved, but multi-thread safety and reproducibility are compromised due to data races
Solution Approach 1:
The patent introduces a guard module as an intermediary between multiple SLMS processes and shared memory resources. This guard module monitors and controls access to memory regions, granting or denying access based on guard conditions. By inserting this intermediary layer, the system enables multi-threaded execution while preventing data races and ensuring reproducible results, thus resolving the contradiction between simulation speed and reproducibility.
2Reliability
If conventional synchronization elements (OS mutexes) are used to ensure multi-thread safety, then reproducibility is improved, but simulation performance deteriorates
Solution Approach 1:
The patent extracts the synchronization functionality from conventional OS mutexes and implements it directly within the SYSTEMC simulation environment through the guard module. This extraction eliminates the overhead of OS-level synchronization while maintaining multi-thread safety. The guard module operates at the memory access level, providing fine-grained control without the performance penalty of traditional mutexes, thus improving simulation performance while maintaining reliability.
Solution Approach 2:
The patent replaces the mechanical OS mutex synchronization mechanism with a software-based guard condition system integrated into the SYSTEMC kernel. Instead of relying on OS-level locking mechanisms that incur significant overhead, the system uses configurable guard conditions that are evaluated at memory access points. This substitution reduces synchronization overhead and improves simulation performance while maintaining multi-thread safety.
3Reliability
If guarded memory access is implemented to prevent data races, then multi-thread safety is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into multiple guarded memory regions, each with its own guard conditions and access rules. Instead of implementing a single complex global synchronization mechanism, the system divides memory access control into smaller, independent units. Each region can be independently configured and managed, reducing the overall system complexity while maintaining multi-thread safety. This segmentation allows for fine-grained control and easier configuration of guard conditions.
Data Source
AI summary
Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.