Guardian Circuit Timeout Monitoring for FSM State Transitions
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Solution Overview
Problem
Finite state machines (FSMs) can get stuck during state transitions due to slow or incomplete transitions, which can lead to operational delays or hangs, especially under power constraints and race conditions, and existing solutions are not sufficiently robust or efficient to address these issues.
Innovation Solution
A guardian circuit module that detects state transitions using a dedicated guardian clock signal and asserts a trigger signal if a transition is not completed within a threshold number of cycles, resetting the FSM to a safe state if the transition takes too long, thereby preventing hangs and ensuring robust operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex high-power monitoring solutions are used to monitor FSM state transitions, then reliability is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent extracts the monitoring function into a separate, dedicated guardian circuit module that operates independently from the main FSM. This guardian circuit monitors state transitions by detecting changes in state signals and uses a dedicated guardian clock to track transition timing, thereby reducing the complexity burden on the main FSM while maintaining reliable monitoring capability.
Solution Approach 2:
The guardian circuit acts as an intermediary between the FSM state signals and the reset control mechanism. It introduces intermediate signals (transition detection signal, timeout signal) that mediate between the raw state transitions and the final reset action, providing a buffered, controlled approach to reliability monitoring without direct complex intervention in the FSM core.
2Reliability
If complex high-power monitoring solutions are used to monitor FSM state transitions, then reliability is improved, but power consumption increases
Solution Approach 1:
The guardian circuit employs a timeout mechanism that uses a limited-count clock counter (N cycles) to monitor state transitions. This disposable-style approach resets the monitoring window after each detected transition, using only the minimal necessary clock cycles to determine timeout conditions, thereby avoiding continuous high-power monitoring while maintaining reliability through periodic checks.
Solution Approach 2:
The monitoring is performed periodically using discrete clock cycles rather than continuous monitoring. The guardian clock generates periodic ticks that advance a counter, and the timeout condition is checked at these periodic intervals. This periodic sampling approach significantly reduces power consumption compared to continuous monitoring while still providing reliable detection of stuck transitions.
3Speed
If timeout threshold is set low for quick reset response, then responsiveness is improved, but false resets increase
Solution Approach 1:
The timeout threshold N is not a fixed value but is dynamically configured based on the specific FSM transition characteristics and timing requirements. This dynamic parameter allows the system to adapt the monitoring sensitivity - setting lower thresholds for fast-transitions to improve responsiveness, and higher thresholds for slower transitions to prevent false resets, thereby optimizing both speed and reliability for different operational contexts.
Data Source
AI summary
A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.