Guest Physical Address Logging for TLB Memory Access Faults
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Solution Overview
Problem
In virtualized computing systems, detecting memory access faults in translation lookaside buffers that perform two-stage address translations often omits intermediate guest physical addresses, necessitating slow and computationally expensive single-stage page table walks by the hypervisor, and requires significant circuit area for storing guest physical addresses in the lookaside buffer.
Innovation Solution
Implementing a sidecar data store to log guest physical addresses associated with fault conditions, allowing hardware-based determination and reducing the need to store these addresses for every entry in the translation lookaside buffer, and using a single-stage page table walk to populate the sidecar with the corresponding guest physical address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guest physical addresses are stored in the translation lookaside buffer for every entry, then fault detection capability is improved, but circuit area increases significantly
Solution Approach 1:
The patent extracts the guest physical address storage function from the main translation lookaside buffer structure. Instead of storing guest physical addresses in every TLB entry, a separate sidecar data store is introduced that only stores these addresses when needed (upon fault conditions), thereby reducing the circuit area while maintaining fault detection capability.
Solution Approach 2:
The patent segments the address storage functionality into two distinct parts: the translation lookaside buffer for virtual-to-physical address translation and the sidecar data store for logging guest physical addresses. This segmentation allows each component to be optimized independently and reduces the overall circuit area required.
2Device complexity
If single-stage page table walks are performed by the hypervisor, then fault handling is simplified, but processing time increases
Solution Approach 1:
The patent performs preliminary action by having the sidecar data store pre-compute and store the guest physical address when a fault condition occurs. This preliminary computation eliminates the need for the hypervisor to perform time-consuming single-stage page table walks during fault handling, thereby reducing processing time while maintaining simplified fault handling procedures.
3Speed
If two-stage address translation is performed in the translation lookaside buffer, then address translation speed is improved, but the need for intermediate guest physical address storage arises
Solution Approach 1:
The patent introduces the sidecar data store as an intermediary mechanism that captures and stores intermediate guest physical address information when needed. This intermediary structure allows the two-stage address translation to proceed at high speed while ensuring that intermediate address information is preserved for fault handling purposes, eliminating information loss.
Data Source
AI summary
Systems and methods are disclosed for logging guest physical address for memory access faults. For example, a method for logging guest physical address includes receiving a first address translation request from a processor pipeline at a translation lookaside buffer for a first guest virtual address; identifying a hit with a fault condition corresponding to the first guest virtual address; responsive to the fault condition, invoking a single-stage page table walk with the first guest virtual address to obtain a first guest physical address; and storing the first guest physical address with the first guest virtual address in a data store, wherein the data store is separate from an entry in the translation lookaside buffer that includes a tag that includes the first guest virtual address and data that includes a physical address.