Guest Root Register Sharing Virtual Machine

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Solution Overview

Problem

Traditional microprocessor virtualization techniques are limited by high hypervisor software processing operations due to frequent exceptions and inefficient resource sharing, which hampers the execution of virtualized guest operating systems.

Innovation Solution

The implementation of guest and root mode control registers that support virtualization of hardware resources, allowing for reduced hypervisor intervention through selective state sharing and concentric modes of control, enabling efficient execution of multiple operating systems without requiring root-mode intervention for common privileged operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional de-privileging virtualization is used, then guest operating systems can run in user mode, but hypervisor software processing operations increase due to frequent exceptions

Engineering Contradiction:
Improveguest OS execution capabilityVSAvoidhypervisor processing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the control register space into guest-accessible registers and root-only registers. Guest mode control registers (GC1-GC3) are separated from root mode control registers (RC0-RC3), allowing guests to independently manage their virtualization state without triggering exceptions to the hypervisor for every register access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces guest mode control registers as intermediaries between the guest OS and the root mode control registers. These intermediate registers cache and manage the state that guests need to access, eliminating the need for frequent exception handling and hypervisor intervention for common privileged operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If full privileged register access is provided to guests, then guest OS functionality is complete, but system security and control are compromised

Engineering Contradiction:
Improveguest OS functionalityVSAvoidsystem security
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by providing different access permissions to different control registers. Guest mode can fully access GC0-GC3 registers for complete OS functionality, while root mode maintains exclusive access to RC0-RC3 registers for security-critical operations, ensuring both functionality and security coexist.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamic access control where the accessibility of control registers changes based on the current execution mode. When in guest mode, GC registers are accessible; when in root mode, RC registers are accessible. This dynamic switching allows flexible functionality while maintaining security boundaries.

Inventive Principle:
Principle #15Dynamics

3Reliability

If frequent hypervisor intervention occurs, then system control is maintained, but computational expense increases

Engineering Contradiction:
Improvesystem controlVSAvoidcomputational expense
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary action by pre-configuring guest mode control registers with the necessary state before guest execution begins. This allows guests to operate independently with cached control information, avoiding the need for frequent hypervisor interventions and reducing computational expense during normal operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9086906B2Apparatus and method for guest and root register sharing in a virtual machine
Publication Date: 2015.07.21 MIPS TECH INC
  • US9086906B2 patent drawing
  • US9086906B2 patent drawing
  • US9086906B2 patent drawing

AI summary

A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.