Guide Pin Wafer for Optical Alignment and EMI Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for aligning guide pins with optical connectors on circuit wafers require separate alignment processes for each die, which is inefficient and costly, especially when dealing with fragile substrate materials.
Innovation Solution
A guide pin wafer with segmented dies and lens cutouts is used, allowing for wafer-scale alignment with a circuit wafer and lens wafer, where guide pins are implanted into a structural base wafer to engage MT or MTP connectors, enabling optical coupling and providing EMI shielding with a lower coefficient of thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate alignment processes are used for each die, then alignment precision may be maintained, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The base wafer is segmented into multiple dies, each die containing multiple guide pins. This segmentation allows the entire wafer to be aligned as a single unit rather than requiring separate alignment processes for each die, thereby reducing manufacturing complexity while maintaining alignment precision through the wafer-scale alignment approach
Solution Approach 2:
Multiple guide pins are combined on a single die, and multiple dies are arranged on a base wafer that is aligned with the circuit wafer at the wafer scale. This merging of multiple alignment functions into a single wafer-scale alignment process reduces the overall complexity of the manufacturing process while maintaining the required precision
2Manufacturing precision
If guide pins are mounted on each individual die, then alignment accuracy for each die is ensured, but production efficiency decreases
Solution Approach 1:
The base wafer is divided into multiple dies, with each die containing multiple guide pins. This segmentation enables parallel processing where multiple dies can be aligned and processed simultaneously at the wafer scale, significantly improving production efficiency while maintaining alignment accuracy through the unified wafer-scale alignment approach
Solution Approach 2:
Multiple guide pins are pre-mounted on each die during wafer fabrication, and the entire base wafer is pre-aligned with the circuit wafer before dicing. This preliminary action eliminates the need for separate alignment operations after dicing, thereby improving production efficiency while ensuring alignment accuracy is maintained throughout the process
3Manufacturing precision
If conventional alignment methods are used, then individual die alignment is achieved, but thermal stability and EMI shielding are compromised
Solution Approach 1:
The base wafer is constructed from a composite structure combining a substrate material with a dielectric material layer. This composite structure provides both the mechanical support needed for wafer-scale alignment and the thermal stability and EMI shielding properties that conventional single-material substrates cannot achieve, while still enabling precise alignment through the wafer-scale process
Data Source
AI summary
A guide pin wafer may include a base wafer that includes multiple dies. Each die may include a corresponding lens cutout. The guide pin wafer may also include multiple guide pins mounted on the base wafer. Each die of the base wafer may be mounted with two or more corresponding guide pins that may be configured to engage a parallel fiber connector to the corresponding die.