Guided Silicon Nanowire Growth for Thin-Film Transistor Contacts
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Solution Overview
Problem
The existing methods for manufacturing nanowires using the planar solid-liquid-solid (IP-SLS) growth technology face challenges in achieving uniform growth and removing disorderly grown nanowires, which affects the yield and performance of thin film transistors by causing overlapping issues with electrodes and increasing contact barriers.
Innovation Solution
A method involving the preparation of an insulating layer, a sacrificial layer with a guide trench, an inducing particle, and a precipitation layer to form nanowires, where the sacrificial layer is modified and removed using ion implantation and plasma processes, allowing for the precise growth and removal of nanowires, improving yield and electrode overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nanowires are grown using IP-SLS growth technology, then the nanowires have monocrystal-like characteristics and good gate control capability, but disorderly grown nanowires cause overlapping issues with electrodes and increase contact barriers
Solution Approach 1:
The patent segments the nanowire growth process by introducing a guide trench structure that divides the growth space into controlled regions. The guide trench, formed by patterning the sacrificial layer, guides nanowire growth along specific paths and prevents disorderly growth. This segmentation approach maintains the monocrystal-like characteristics while eliminating overlapping issues with electrodes.
Solution Approach 2:
The patent introduces a guide trench as an intermediary structure between the substrate and the nanowire growth region. This guide trench acts as a mediator that directs nanowire growth along desired paths, preventing direct contact between disorderly grown nanowires and electrodes, thus reducing contact barriers and overlapping issues while preserving gate control capability.
2Productivity
If disorderly grown nanowires are present, then nanowire yield decreases, but removing them increases process complexity
Solution Approach 1:
The patent applies preliminary action by forming the guide trench structure before nanowire growth occurs. The guide trench is created by patterning the sacrificial layer prior to nanowire deposition, establishing growth guidance pathways in advance. This preliminary structuring prevents disorderly growth from occurring, thereby maintaining high nanowire yield without requiring additional complex removal processes.
Solution Approach 2:
The patent extracts the harmful element (disorderly grown nanowires) by preventing their formation through the guide trench structure. Rather than attempting to remove disorderly grown nanowires after growth, the guide trench extracts the root cause of disorderly growth by confining nanowire growth to specific guided paths, thereby maintaining high yield without increasing process complexity.
3Reliability
If nanowires overlap with electrodes, then contact barriers increase, but adjusting nanowire position reduces growth control
Solution Approach 1:
The patent applies local quality by creating localized guidance structures (guide trenches) at specific positions where nanowire growth needs to be controlled. The guide trench pattern is designed to provide local guidance exactly where needed to prevent electrode overlap, while allowing nanowire growth to proceed with monocrystal-like characteristics in the guided regions. This localized approach improves contact characteristics without compromising overall growth control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the yield of nanowires, improves the overlap between nanowires and electrodes, reduces contact barriers, and increases the mobility of silicon nanowires, leading to better performance in thin film transistors.
Implementation Method 1
processing the precipitation layer to precipitate silicon in the precipitation layer along the guide trench under the induction of the inducing particle to form a silicon nanowire
Implementation Method 2
precipitate silicon in the precipitation layer along the guide trench under the induction of the inducing particle
Implementation Method 3
modifying the sacrificial layer by an ashing process using oxygen plasma
Implementation Method 4
processing the sacrificial layer through an ion implantation so as to form a porous structure in a surface layer of the sacrificial layer away from the substrate
Implementation Method 5
reducing the patterned catalytic layer by using a plasma enhanced chemical vapor deposition process to form the inducing particle
Data Source
AI summary
The present disclosure provides a method for manufacturing a nanowire, a method for manufacturing a thin film transistor, a thin film transistor and a semiconductor device. The method for manufacturing the nanowire includes: preparing an insulating layer on a first surface of a substrate; preparing a sacrificial layer on a surface of the insulating layer away from the substrate, and patterning the sacrificial layer to form a guide trench; preparing an inducing particle in the guide trench; preparing a precipitation layer on a surface of the sacrificial layer away from the substrate and in the guide trench, the precipitation layer covering the inducing particle; processing the precipitation layer to precipitate a preset element in the precipitation layer along the guide trench under an induction of the inducing particle to form a nanowire; and removing the sacrificial layer.