Guided PCB Edge Pads for High-Speed Signal Integrity
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Solution Overview
Problem
Existing circuit board connectors experience significant parasitic artifacts that degrade signal integrity as signal speeds increase, particularly at the interface between pads on the edge of a circuit board and pins of a connector.
Innovation Solution
The formation of conductive pads within channels in the dielectric layers of a circuit board, allowing direct coupling of internal conductive layers to connector pins, thereby reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional approaches are used to couple pads at the edge of a circuit board to pins of a connector, then the structure is simple and easy to manufacture, but parasitic artifacts increase and signal integrity deteriorates
Solution Approach 1:
The pad structure transitions from a traditional planar configuration to a three-dimensional configuration by forming the pad within a channel that extends through dielectric layers. This vertical dimensionality change allows the pad to be positioned closer to the connector pins while maintaining electrical isolation, thereby reducing parasitic artifacts and improving signal integrity without proportionally increasing manufacturing complexity.
Solution Approach 2:
The circuit board structure is segmented into distinct functional regions: the channel portion that provides mechanical guidance and alignment, the pad portion that provides electrical connection, and the dielectric layers that provide isolation. This segmentation allows each component to be optimized independently for its specific function, reducing overall parasitic effects while maintaining manufacturability.
2Productivity
If signal speed is increased to improve data processing capability, then productivity increases, but parasitic artifacts have more significant impact on signal quality
Solution Approach 1:
The channel structure is designed in advance to counteract the harmful effects of high-speed signaling by providing a controlled electromagnetic environment. The channel walls and dielectric materials are configured to minimize parasitic capacitance and inductance before signals are transmitted, thereby maintaining signal quality even at increased data processing speeds.
3Reliability
If vias are used to connect internal conductive layers to the board edge, then the manufacturing process is traditional and well-established, but parasitic artifacts are introduced that degrade signal integrity
Solution Approach 1:
The invention extracts and eliminates the via component from the signal path by forming the pad directly within a channel that extends to the board edge. This removes the via-induced parasitic artifacts while the channel formation process can be integrated into existing manufacturing workflows, maintaining ease of manufacture while improving signal integrity.
Data Source
AI summary
A circuit board may include a plurality of electrically-conductive layers separated and supported by a plurality of dielectric layers of insulating material laminated together and a channel formed at an edge of the circuit board through at least one dielectric layer of the plurality of dielectric layers within which an electrically-conductive pad is formed from an internal electrically-conductive layer of one of the plurality of electrically-conductive layers.