Integrated Circuit Error Detection With Guided Random Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Hardware errors in integrated circuits, such as silent data corruption, are difficult to detect using deterministic or pseudo-random tests, leading to reliability and uptime issues in computing devices, especially in server farms.
Innovation Solution
Employ guided on-target random test-generation techniques using directed random tests based on test templates, multi-pass consistency checking, and switching logical roles of processing cores to enhance error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deterministic or pseudo-random tests are used to detect hardware errors, then the testing process is simple and fast, but the detection coverage is insufficient and cannot detect intermittent errors
Solution Approach 1:
The system performs preliminary actions by executing the same test case multiple times (multi-pass testing) before concluding whether an error exists. Each pass uses different random seeds to generate varied test inputs, allowing intermittent errors to manifest. This preliminary repeated execution before final error determination resolves the contradiction by enhancing detection capability without requiring fundamentally more complex testing infrastructure.
Solution Approach 2:
The testing system dynamically adapts by switching between deterministic and random testing modes, and by varying random seeds across multiple passes. This dynamic approach allows the system to maintain relatively simple test structures while achieving comprehensive error detection coverage, including intermittent errors that static deterministic tests would miss.
2Reliability
If more comprehensive testing methods are used to detect hardware errors, then error detection coverage improves, but the testing time and complexity increase
Solution Approach 1:
The system applies partial action by executing test cases a specific number of times (e.g., 3-5 passes) rather than exhaustive continuous testing. This provides sufficient coverage to detect intermittent errors while avoiding excessive time consumption. The multi-pass approach with moderate repetition achieves the balance between detection coverage and time efficiency.
Solution Approach 2:
The testing methodology uses periodic action by systematically repeating test cases at regular intervals with different random seeds. This periodic structure enables comprehensive error detection over time without requiring continuous exhaustive testing, thus reducing overall testing time while maintaining high detection coverage.
3Measurement precision
If random tests with multiple passes are used, then intermittent hardware errors can be detected, but the testing overhead increases
Solution Approach 1:
The system performs preliminary repeated executions with varying random inputs before making error determination. This preliminary multi-pass action increases measurement precision for detecting intermittent errors while managing overhead through a structured, limited number of passes rather than unbounded testing.
Solution Approach 2:
The testing system uses copying by replicating test cases across multiple passes with different random seeds. This copying approach enables precise error detection through varied execution contexts while managing overhead by reusing the same test case structures rather than creating entirely new complex tests for each pass.
Data Source
AI summary
Hardware errors can be detected by generating a plurality of test templates to perform testing on an integrated circuit (IC) device. A set of random tests can be generated corresponding to the plurality of test templates. The set of random tests can be executed on the IC device for multiple passes, and the results of the multiple passes can be compared to detect the hardware error in the IC device. The set of random tests can be generated as a binary image for execution on the IC device. The IC device may include multiple processing cores, and executing the multiple passes may include changing logical role of each processing core between subsequent passes. The set of random tests can be executed in a bare-metal mode, or at an application level of the IC device.