H-Bridge Current Transmitter with Staggered Switching for EMI Reduction
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Solution Overview
Problem
Existing driver circuits face challenges in achieving fast switching times for improved digital signal quality while minimizing electromagnetic interference (EMI), as faster switch times often degrade signal quality and require large capacitors that are difficult to control across PVT variations.
Innovation Solution
A driver circuit with a staggered voltage development mechanism, utilizing pairs of switches of different polarities and timing circuitry to apply input signals in a staggered manner, reducing the need for extensive delay elements and allowing for faster switching times without excessive EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fast switching times are used to improve signal quality, then digital signal quality is improved, but electromagnetic interference increases
Solution Approach 1:
The patent divides the single switching event into multiple sequential switching events by splitting the current path into multiple segments. Each segment switches in succession rather than simultaneously, which distributes the EMI-generating transitions over time while maintaining the overall signal transition. This segmentation of the switching process reduces peak EMI while preserving signal quality.
Solution Approach 2:
The patent employs periodic switching actions across multiple current paths, where each path switches at a staggered time interval. This periodic distribution of switching events transforms a single high-EMI event into multiple lower-EMI events spaced in time, reducing overall electromagnetic interference while maintaining fast effective switching for signal quality.
2Object-generated harmful factors
If RC slew rate control is used to reduce EMI, then electromagnetic interference is reduced, but large capacitors are required that are difficult to control across PVT variations
Solution Approach 1:
The patent extracts and removes the large capacitor requirement from the EMI reduction mechanism. Instead of using RC time constants with large capacitors, the invention achieves EMI reduction through the topological restructuring of multiple current paths with staggered switching, eliminating the need for PVT-sensitive large capacitors while maintaining EMI suppression.
Solution Approach 2:
The patent substitutes the passive RC capacitor-based EMI control mechanism with an active multi-path current switching mechanism. This replacement eliminates reliance on capacitor values that are sensitive to PVT variations, using instead the controlled timing and topology of multiple current paths to achieve EMI reduction.
3Object-generated harmful factors
If staggered voltage development with multiple switch pairs is used, then EMI is reduced and signal quality is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple current paths into a unified H-bridge structure that shares common components such as the load, current sources, and control logic. By combining these paths within a single integrated circuit framework, the complexity is managed through modular design rather than requiring completely separate circuits for each current path.
Data Source
AI summary
The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.