H-Matrix Parity Circuit for High-Capacity Memory Error Correction
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Solution Overview
Problem
As semiconductor memory devices increase in capacity, it becomes challenging to fabricate memory devices without defective memory cells, leading to the need for error correction techniques such as redundant memory cells and error correction circuits to address errors in memory systems.
Innovation Solution
An error processing circuit is designed with H matrix calculation circuits for generating parities during encoding and decoding operations, syndrome calculation for error detection, and correction circuits to efficiently correct errors in memory systems by utilizing first and second H matrices for upstream and downstream data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The H matrix is divided into multiple sub-matrices (first H matrix and second H matrix), allowing the error correction process to be segmented into separate calculations. This segmentation enables more efficient handling of larger memory capacities while maintaining reliability through distributed parity generation and syndrome calculation.
Solution Approach 2:
Parity bits serve as intermediary elements that mediate between the data bits and error detection/correction. The patent generates multiple sets of parity bits using different H matrices, creating intermediate parity information that facilitates reliable error correction in high-capacity memory systems.
2Reliability
If error correction capability is enhanced, then reliability is improved, but circuit complexity increases
Solution Approach 1:
The error correction circuit is segmented into specialized units: first H matrix calculation circuit, second H matrix calculation circuit, parity calculation circuit, syndrome calculation circuit, and correction circuit. Each unit performs a specific function, reducing overall circuit complexity through functional decomposition while maintaining enhanced error correction capability.
Solution Approach 2:
The patent generates multiple sets of parity bits (excessive action) using different H matrices, providing redundant error correction information. This partial redundancy enables more robust error correction without requiring a complete redesign of the error processing circuit.
3Measurement precision
If multiple H matrices are used for error correction, then error correction accuracy is improved, but calculation overhead increases
Solution Approach 1:
The calculation process is segmented into parallel operations: first H matrix calculation and second H matrix calculation can be performed simultaneously, with their results combined by the parity calculation circuit. This segmentation reduces calculation overhead by enabling parallel processing while maintaining high error detection accuracy.
Solution Approach 2:
Parity bits are calculated in advance during the encoding operation using multiple H matrices, preparing error correction information before data storage. This preliminary action reduces decoding time during read operations, as the syndrome calculation can proceed efficiently with pre-computed parity information.
Data Source
AI summary
An error processing circuit includes: a first H matrix calculation circuit configured to calculate a first H matrix and upstream data to generate a partial first parity, during an encoding operation; a second H matrix calculation circuit configured to calculate a second H matrix and the upstream data to generate a second parity, during the encoding operation; and a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the encoding operation.