H-Shaped Buried Conductive Layer for Trench Capacitor Seam Reduction
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Solution Overview
Problem
In the fabrication of semiconductor memory devices with vertical transistors and trench capacitors, issues such as divots on the filling electrode and seams in the buried conductive layer affect performance and reliability due to over etching and seam generation, which impact the connection between the vertical transistor and the trench capacitor.
Innovation Solution
A method involving the formation of a trench capacitor with a collar dielectric layer and a conformally deposited barrier layer, followed by a conductive layer and a buried strap definition layer, where the conductive layer is etched using the buried strap definition layer as an etching stop to create an H-shaped buried conductive layer, reducing seam formation and improving electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If over etching is performed to completely remove etched films, then the filling electrode is fully formed, but divots are formed on the filling electrode and tip is formed at the interface to generate point discharge
Solution Approach 1:
The patent introduces an etch stop layer beneath the filling electrode that is designed to be etched at a different rate than the surrounding films. This preliminary structural action prevents complete removal of the filling electrode material, maintaining its integrity while still allowing sufficient etching to form the desired structure. The etch stop layer acts as a pre-planned barrier that stops the etching process before divots and tips form, eliminating point discharge issues.
2Reliability
If polysilicon layer is filled into the region between filling electrode and sidewalls to form buried conductive layer, then connection between vertical transistor and trench capacitor is established, but seams are generated in the buried conductive layer
Solution Approach 1:
The patent introduces a collar dielectric layer as an intermediary structure that surrounds the filling electrode layer. This collar dielectric layer provides a controlled interface between the filling electrode and the sidewalls, allowing the buried conductive layer to be formed without direct contact issues that cause seams. The collar dielectric acts as a mediator that ensures uniform filling and eliminates voids or seams in the buried conductive layer while maintaining electrical connection.
3Area of stationary object
If vertical transistor structure is adopted to save space, then integration density is improved, but fabrication complexity increases due to additional layers and processes
Solution Approach 1:
The patent segments the vertical transistor structure into distinct functional layers: filling electrode layer, collar dielectric layer, etch stop layer, and buried conductive layer. Each layer serves a specific purpose and can be fabricated using standardized deposition and etching processes. This segmentation allows complex 3D structures to be built through sequential simple processes, reducing overall fabrication complexity while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of the memory device by reducing seam formation and eliminating point discharges, ensuring stable electrical connections between the trench capacitor and the vertical transistor.
Implementation Method 1
A barrier layer is conformally formed on the collar dielectric layer, the filling electrode layer and sidewalls of the trench
Implementation Method 2
A conductive layer is conformally deposited on the barrier layer
Data Source
AI summary
A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.