H-Shaped VFET Fin Structure for Increased Current Drivability
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Solution Overview
Problem
Vertical field effect transistors (VFETs) face challenges in maintaining current drivability as feature sizes shrink, leading to degraded device speed and performance, necessitating techniques to enhance current drivability without increasing cell area.
Innovation Solution
The method involves forming a fin structure in VFET devices by depositing a hardmask and mandrel material, patterning, and selectively removing mandrels to create a ladder-shaped pattern, which is transferred to the substrate to form interconnected fins, thereby increasing the effective channel width without expanding the cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are shrunk to continue CMOS scaling, then device density is improved, but current drivability is degraded
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertical 3D fin channel structures. By growing fins vertically from the substrate and wrapping gates around these fins, the channel extends in the vertical dimension rather than purely lateral, enabling higher device density while maintaining adequate current drivability through increased effective channel width via multiple fins per device.
Solution Approach 2:
The patent divides the channel into multiple discrete fin segments (first fin, second fin, third fin) rather than using a single continuous planar channel. Each fin acts as an independent current path, allowing the total effective channel width to be increased by adding more fin segments without proportionally increasing the lateral cell area.
2Productivity
If effective channel width is increased to improve current drivability, then device speed is improved, but cell area is increased
Solution Approach 1:
The patent resolves this contradiction by moving the channel expansion from the lateral plane to the vertical dimension. Multiple fins are grown vertically from the substrate, increasing the effective channel width without requiring proportional increases in lateral cell area. The gate wraps around these vertical fins, maintaining control while achieving higher current drivability in a compact footprint.
Solution Approach 2:
The patent merges multiple fin structures into a single integrated VFET device. The first fin, second fin, and third fin are combined under a common gate structure, creating one device with increased effective channel width. This merging allows the device to achieve higher current drivability equivalent to multiple separate devices while occupying the area of a single device.
Data Source
AI summary
Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.