H-Tree Clock Distribution for Structured ASIC Flip-Flop Density
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Solution Overview
Problem
Current structured ASICs face challenges in maintaining high flip-flop density and minimizing clock skew while optimizing routing resources, which affects performance and efficiency in integrated circuit design.
Innovation Solution
The implementation of an H-tree structure in a structured ASIC, with a base array and custom conducting layers, minimizes clock skew and increases flip-flop density by balancing path-lengths and loads, and allows for prefabricated conducting layers to free up resources for other routing needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional routing methods are used in structured ASICs, then routing flexibility is maintained, but clock skew increases and flip-flop density decreases
Solution Approach 1:
The patent segments the routing structure into H-trees and V-trees, dividing the clock distribution network into hierarchical segments. This segmentation allows for balanced path lengths to reduce clock skew while maintaining the ability to place flip-flops at tree intersections to increase density
Solution Approach 2:
The patent introduces a two-dimensional routing structure combining H-trees (horizontal) and V-trees (vertical) to create a grid-like topology. This dimensional approach enables more efficient space utilization and shorter, more balanced routing paths compared to traditional one-dimensional routing, thereby reducing clock skew and increasing flip-flop density
2Adaptability or versatility
If more conducting layers are added to increase functionality, then device capability improves, but manufacturing complexity increases
Solution Approach 1:
The patent designs conducting layers to serve multiple functions: H-trees and V-trees collectively provide both clock distribution and data routing capabilities. This multi-functionality reduces the need for separate dedicated layers, thereby increasing device capability while controlling manufacturing complexity
Solution Approach 2:
The patent implements a hierarchical routing structure where H-trees and V-trees are nested within each other to form a compact two-dimensional array. This nesting approach allows multiple routing functions to be integrated within a limited number of conducting layers, enhancing versatility without proportionally increasing manufacturing complexity
3Adaptability or versatility
If custom conducting layers are formed for each customer requirement, then customization improves, but fabrication time increases
Solution Approach 1:
The patent implements a two-stage fabrication process where H-trees and V-trees are formed in preliminary conducting layers before final custom routing. This preliminary action establishes the foundational routing infrastructure that can be quickly customized for different applications without requiring complete re-fabrication, thereby reducing fabrication time while maintaining customization capability
Solution Approach 2:
The patent creates a dynamic routing architecture where the topmost conducting layer can be customized for different customer requirements while the underlying H-tree and V-tree structure remains fixed. This dynamic approach allows rapid reconfiguration for different applications without affecting the entire device, reducing fabrication time for customizations
Data Source
AI summary
An H-tree is formed in a conducting layer over a base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of a base array and H-tree. The endpoints of an H-tree can be formed at or near sequential elements. When an H-tree is used as part of a clock structure, clock skew to sequential elements and consumption of routing resources for forming a clock structure can be minimized. When a pulse generator is coupled to an H-tree, at least one flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.