H.264 Scalable Video Decoder Layer Switching Memory Optimization
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Solution Overview
Problem
Conventional H.264 SVC decoders require significant memory space to store base layer information, leading to increased chip die size when implemented on-chip and limited system performance due to high bus bandwidth requirements for external memory access.
Innovation Solution
A video processing circuit that decodes H.264 SVC bitstreams using a minimal amount of memory by decoding only a predetermined amount of base layer picture macroblock rows for a target layer picture macroblock row, allowing for on-chip memory implementation and reducing the need for external memory access, while supporting spatial scalability through layer switching and parallel processing of coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire base layer stream is decoded and all base layer information is stored in memory, then the target layer stream can be decoded using this information, but a significant amount of memory space is required
Solution Approach 1:
The patent extracts only the necessary base layer information (coefficients of base layer macroblock rows) required for target layer decoding, rather than storing all base layer data. This selective extraction reduces memory requirements while maintaining decoding accuracy by keeping only the essential predictive data needed for spatial scalability.
Solution Approach 2:
The patent segments the base layer information storage into smaller units (base layer macroblock rows) rather than storing the entire base layer picture. This segmentation allows the decoder to store and manage information in manageable chunks, reducing overall memory space requirements while enabling efficient access during target layer decoding.
2Quantity of substance
If base layer information is stored on external memory, then memory space is available, but system performance is limited by bus bandwidth
Solution Approach 1:
The patent transitions from external memory storage to on-chip memory by changing the dimensional aspect of memory architecture. By reducing the data volume to only essential base layer coefficients and utilizing on-chip memory resources, the system eliminates the external bus bandwidth bottleneck while maintaining sufficient storage capacity for decoding operations.
3Productivity
If base layer information is stored on chip memory, then system performance improves, but chip die size increases
Solution Approach 1:
The patent extracts only the minimal necessary base layer information (coefficients of base layer macroblock rows) required for spatial scalable decoding, eliminating redundant data storage. This selective extraction enables on-chip memory implementation with reduced memory capacity requirements, thereby avoiding significant increases in chip die size while maintaining performance benefits.
4Reliability
If conventional layer-by-layer decoding is used, then decoding completeness is achieved, but memory bandwidth requirements increase
Solution Approach 1:
The patent applies partial action by decoding and storing only the necessary portion of base layer information (specific macroblock row coefficients) rather than the entire base layer picture. This partial decoding approach provides sufficient data for spatial scalable decoding while significantly reducing memory bandwidth requirements compared to conventional complete base layer decoding.
Data Source
AI summary
An apparatus comprising a decoder circuit, a memory circuit and a processing circuit. The decoder circuit may be configured to generate a first intermediate signal having a plurality of coefficients of a target layer and a plurality of coefficients of a base layer, in response to an input bitstream. The memory circuit may be configured to (i) store the first intermediate signal and (ii) present (a) a second intermediate signal comprising the plurality of coefficients of the target layer or (b) a third intermediate signal comprising the plurality of coefficients of the base layer. The processing circuit may be configured to (i) switch a plurality of times between the coefficients of the target layer and the coefficients of the base layer while reading a frame from the memory circuit, (ii) transform the coefficients of the base layer into base layer information, (iii) buffer the base layer information, where the base layer information buffered at any time comprises at most a subset of macroblock rows of the frame and (iv) generate an output signal comprising a plurality of target layer samples in response to the second intermediate signal and the base layer information as buffered.