Half-Bridge Cascode Layout to Reduce Parasitic Inductance
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Solution Overview
Problem
Existing half-bridge semiconductor devices with cascode arrangements suffer from DC power and switching losses due to inductance effects in wire connections, leading to gate bounce and increased device resistances, which hinder high-frequency operation and power density in switched mode applications.
Innovation Solution
A discrete half-bridge semiconductor device is designed with a stacked and flipped configuration of high voltage and low voltage transistor dies, where the source of the high voltage die is directly connected to the drain of the low voltage die, and the gate of the high voltage die is connected to the source of the low voltage die, using common conductive members to reduce parasitic inductances and resistances, and eliminate the need for external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire connections are used to connect cascode arrangements in a half-bridge configuration, then the device can be assembled with external connections, but parasitic inductances and resistances increase causing DC power losses, switching losses, and gate bounce
Solution Approach 1:
The patent merges the two separate cascode arrangements into a single integrated half-bridge device package, eliminating external wire connections between them. The internal direct connections between the cascode arrangements remove parasitic inductances and resistances associated with external wire bonds, thereby reducing DC power losses and switching losses while maintaining manufacturing feasibility through a unified assembly process
Solution Approach 2:
The patent introduces a common connection pad structure that serves as an intermediary element to directly connect the source of the first high voltage device to the drain of the second low voltage device. This common connection pad acts as a low-inductance intermediary that eliminates the need for external wire connections while providing a stable electrical connection point, thereby reducing parasitic effects and power losses
2Ease of operation
If wire connections are used to connect cascode arrangements, then external connections can be established, but gate bounce occurs due to inductance effects during high frequency switching
Solution Approach 1:
By merging the cascode arrangements into a single integrated device with internal direct connections, the patent eliminates the inductance effects of external wire connections that cause gate bounce during high-frequency switching. The unified structure ensures stable switching operation while maintaining ease of connection through a single integrated component
3Adaptability or versatility
If two separate device packages are used to form a half-bridge arrangement, then manufacturing can be optimized for each device independently, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent combines two separately optimized cascode arrangements into a single integrated half-bridge device package. This merging maintains the individual optimization benefits of each cascode arrangement (high voltage device with low voltage device) while eliminating the complexity of assembling and connecting two separate packages, thereby reducing overall manufacturing complexity and external connection requirements
Data Source
Figure 1
Figure 2a~2b
Figure 2c~2d
AI summary
This disclosure relates to a discrete half bridge semiconductor device comprising: a first cascode arrangement and a second cascode arrangement; each of the first cascode and second cascode arrangements comprising a high voltage FET device die and a low voltage FET device die; wherein the source of the high voltage FET device die is mounted on and connected to a drain of the low voltage FET device die; and the source of the low voltage FET device die and gate of the high voltage FET device die are connected to a drain terminal of the high voltage FET device die of the second cascode arrangement at common connection pad.