Half-Bridge Control Circuit Digital Feedback Loop
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Solution Overview
Problem
Existing half-bridge circuits face challenges in accurately generating a pure PWM signal with a constant switching period and synchronization issues due to the introduction of dead-times, leading to suboptimal output voltage control, especially when using n-channel FETs and digital implementations like sigma-delta converters.
Innovation Solution
A half-bridge control circuit with a selector circuit, digital subtractor, digital integrator, down-scale circuit, sampling circuit, and pulse generator, which generates a pulsed signal based on feedback and reference signals to control electronic switches, eliminating the need for high-resolution ADCs and ensuring synchronization, thereby achieving precise output voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dead-times are introduced to avoid simultaneous switching of T1 and T2, then switching safety is improved, but synchronization between input signal and output voltage deteriorates
Solution Approach 1:
The control circuit proactively compensates for dead-time effects by adjusting the PWM duty cycle in advance based on the state of the half-bridge switches. When a switch is in dead-time, the controller pre-adjusts the output to account for the expected voltage level, thereby maintaining synchronization without eliminating the necessary dead-time safety margin.
Solution Approach 2:
The system implements feedback control where the actual output voltage is monitored and used to adjust subsequent PWM signals. This closed-loop approach compensates for distortions introduced by dead-times, ensuring that the output voltage remains synchronized with the input signal while maintaining the safety benefits of dead-time insertion.
2Device complexity
If simple inversion method is used to generate HS and LS signals, then device complexity is reduced, but output voltage control precision deteriorates
Solution Approach 1:
The patent replaces complex analog control circuits with a digital control implementation. A microcontroller or digital signal processor generates the PWM signals and controls the half-bridge switches, substituting mechanical/analog signal inversion with digital logic and software-based control algorithms that achieve higher precision.
Solution Approach 2:
The system dynamically adjusts PWM duty cycle parameters based on feedback from voltage sensing circuits. By changing the duty cycle parameter in response to load conditions and voltage deviations, the digital control system achieves precise output voltage regulation without requiring complex analog circuitry.
3Device complexity
If sigma-delta converter is used for digital implementation, then ADC resolution requirements are reduced, but switching period constancy deteriorates
Solution Approach 1:
The control system employs a dedicated timer or counter that generates PWM signals with a fixed switching period independent of the sigma-delta modulation process. This separate timing mechanism ensures constant switching frequency while the sigma-delta converter handles the voltage regulation through variable duty cycle adjustment within each period.
Solution Approach 2:
The control architecture separates the switching frequency generation function from the voltage regulation function. The timer/counter segment handles periodic switching at constant frequency, while the sigma-delta converter segment independently adjusts the duty cycle to achieve precise voltage control, allowing both functions to optimize their respective performance.
Data Source
AI summary
A method of controlling a half-bridge circuit includes receiving an analog feedback signal proportional to an output of the half-bridge circuit, comparing the received analog feedback signal with a threshold value, selecting a digital feedback signal based on a result of the comparing, comparing the digital feedback signal with a digital reference signal to generate a digital error signal, integrating the digital error signal to generate an integration error signal, downscaling the integral error signal to generate a downscaled integration signal, sampling the downscaled integration signal to generate a sampled integration signal, and generating pulsed signals from the sampled integration signal to provide an input to the half-bridge circuit.