Half-Bridge Converter Timing for Zero-Voltage Switching

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Solution Overview

Problem

Resonant power converters face challenges in accurately controlling non-overlap times at higher frequencies, leading to hard-switching and reduced efficiency and lifespan of switching elements due to delays in controller operations.

Innovation Solution

A converter circuit with a controller that adjusts non-overlap times by sending command signals based on regulated times calculated from measured and target times, ensuring the high-side and low-side switches are turned on before the end of the rising and falling edges of the half-bridge node voltage, minimizing delays and preventing hard-switching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the operating frequency of resonant power converters is increased to reduce size, then the converter size is reduced, but hard-switching occurs due to controller delays, reducing efficiency and lifespan of switching elements

Engineering Contradiction:
Improveconverter sizeVSAvoidswitching element lifespan
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The controller predicts the optimal turn-on moment for switches by measuring the actual rising/falling edge durations and calculating regulated times in advance. This preliminary calculation ensures switches are turned on at the precise moment voltage reaches zero, preventing hard-switching even at high frequencies where controller delays would normally cause timing errors.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts non-overlap times based on measured voltage edge characteristics. By continuously measuring actual rising and falling edge durations and recalculating regulated times, the controller adapts to varying operating conditions and frequency changes, maintaining accurate zero-voltage switching timing despite high-frequency operation and component tolerances.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If fixed non-overlap times are used in controller design, then the device complexity is reduced, but manufacturing variations and temperature effects cause timing inaccuracies, leading to hard-switching

Engineering Contradiction:
Improvecontroller design complexityVSAvoidswitching timing accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The controller measures actual voltage rising and falling edge durations in real-time and uses this feedback to calculate regulated times. This closed-loop approach compensates for manufacturing variations in component values and temperature-induced parameter changes, ensuring accurate timing without requiring overly precise fixed time constants or complex calibration procedures.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system uses its own operational characteristics (measured voltage edge durations) to automatically adjust its control parameters (regulated times). This self-calibration eliminates the need for external calibration equipment or complex manufacturing tolerance control, allowing the converter to automatically adapt to its actual operating conditions.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4482006A1Converter circuit
Publication Date: 2024.12.25 NXP USA INC
  • EP4482006A1 patent drawingFigure 1
  • EP4482006A1 patent drawingFigure 2
  • EP4482006A1 patent drawingFigure 3

AI summary

One example discloses a converter circuit, including: an input configured to receive either a voltage or a current; an output configured to transmit either a voltage or a current; a voltage reference; a half-bridge (HB) node; a high-side (HS) switch coupled between the input and the HB node; a low-side (LS) switch coupled between the voltage reference and the HB node; and a controller coupled to the HB node, the HS switch, and the LS switch; wherein the controller is configured to send a first command signal after a first regulated time to turn on the HS switch after an HB voltage on the HB node begins rising in response to the LS switch having been turned off.