Half-Bridge Power Module Layout for Balanced Current Sharing
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Solution Overview
Problem
Current sharing mismatch between parallel-connected transistors in power semiconductor device modules due to differences in conduction paths, leading to gate signal oscillation and reduced electrical efficiency.
Innovation Solution
Implementing a half-bridge circuit power module with symmetric current conduction paths by using separate conductive clips to couple each transistor to a common drain configuration, balancing current path lengths and reducing impedance differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate conductive clips are used to couple each transistor to a common drain configuration, then current sharing balance is improved, but device complexity increases
Solution Approach 1:
The patent divides the electrical connection system into separate conductive clips for each transistor (first conductive clip for first high-side transistor, second conductive clip for second high-side transistor, etc.). This segmentation ensures that each transistor has its own dedicated current path to the common drain, eliminating current sharing mismatch while maintaining a manageable structural complexity through modular connection elements.
2Stability of the object's composition
If symmetric current conduction paths are implemented, then gate signal oscillation is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric placement of conductive clips and patterned metal layers to achieve symmetric current conduction paths. By strategically positioning each conductive clip and corresponding metal layer, the design creates equal electrical path lengths for parallel-connected transistors, thereby balancing impedance and reducing gate signal oscillation while working within manufacturing constraints.
3Loss of energy
If multiple patterned metal layers are used to balance impedance, then electrical efficiency is improved, but device complexity increases
Solution Approach 1:
The patent utilizes multiple patterned metal layers disposed at different positions on the substrate to create balanced impedance paths. By distributing metal layers (first patterned metal layer, second patterned metal layer, third patterned metal layer) across different spatial dimensions and coupling them with specific conductive clips, the design achieves impedance balancing that reduces energy loss while maintaining a structured, multi-layer architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves current sharing balance and reduces gate oscillation, enhancing the electrical efficiency of the power module.
Implementation Method 1
a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer
Data Source
AI summary
In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.