Half-Bridge Gate Driver Circuit for Shorter Dead-Time Switching

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Solution Overview

Problem

Existing power converters face significant challenges in managing dead-time transitions due to the risk of shoot-through currents and high losses associated with reverse conduction modes, particularly in wide band gap devices like SiC and GaN, which are not effectively addressed by current control methods that often require complex circuits, additional sensors, or increase stray inductance.

Innovation Solution

A gate driver circuit with current mirroring circuits is used to provide early gate pull-up commands through galvanic insulation, reducing dead-time duration by sensing gate current and transferring it to the opposite switch, ensuring precise control without causing perturbations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dead-time is extended to prevent shoot-through currents, then device reliability is improved, but power losses increase due to reverse conduction

Engineering Contradiction:
Improvedevice reliabilityVSAvoidpower losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by detecting the gate voltage transition of the first switch and提前 (in advance) generating the gate drive signal for the second switch before the dead-time period ends. This early triggering reduces the reverse conduction time of the body diode, thereby reducing power losses while maintaining reliable operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback by monitoring the gate voltage of the first switch and using this information to control the timing of the second switch's gate drive signal. The detection circuit provides feedback about the switching state, allowing dynamic adjustment of the dead-time duration based on actual device behavior rather than using a fixed conservative value.

Inventive Principle:
Principle #23Feedback

2Loss of energy

If dead-time is reduced to minimize power losses, then energy efficiency is improved, but the risk of shoot-through currents increases

Engineering Contradiction:
Improvepower lossesVSAvoidshoot-through risk
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent employs feedback by continuously monitoring the gate voltage of the first switch and using this real-time information to determine when to trigger the second switch. This feedback mechanism ensures that the second switch is only triggered when it is safe to do so, preventing shoot-through currents while allowing minimal dead-time.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit performs preliminary detection of the first switch's gate voltage transition and prepares the second switch's gate drive signal in advance. This preliminary action allows the system to minimize dead-time while maintaining safety margins against shoot-through by ensuring the first switch has fully turned off before the second switch turns on.

Inventive Principle:
Principle #10Preliminary action

3Loss of energy

If smart control methods with look-up tables are used to reduce dead-time, then power losses are reduced, but controller complexity and cost increase

Engineering Contradiction:
Improvepower lossesVSAvoidcontroller complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent extracts the dead-time optimization function from the main controller by implementing a dedicated detection circuit and gate drive circuit that autonomously perform the timing optimization. This extraction eliminates the need for complex microcontroller-based look-up table methods, reducing controller complexity and cost while achieving the same power loss reduction.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses a simplified copying approach by directly detecting the gate voltage transition and replicating the timing information to control the second switch, rather than using complex computational methods. This analog/direct copying method achieves precise timing control without requiring fast computation capabilities or expensive controllers.

Inventive Principle:
Principle #26Copying

4Productivity

If additional sensors and microcontrollers are used for dead-time optimization, then switching performance is improved, but device complexity and cost increase

Engineering Contradiction:
Improveswitching performanceVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the essential sensing function by using the existing gate drive circuitry to detect gate voltage transitions, rather than adding separate current or voltage sensors. This extraction achieves accurate switching timing information without the complexity and cost of additional sensors and microcontrollers.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The gate drive circuit serves itself by using its own output signal (the gate voltage it generates) as the sensing input for timing the complementary switch. This self-service approach eliminates the need for external sensors and complex control systems, achieving improved switching performance with minimal added complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250330166A1Gate driver circuit and process for reducing dead time duration upon switching
Publication Date: 2025.10.23 MITSUBISHI ELECTRIC CORP
  • US20250330166A1 patent drawing
  • US20250330166A1 patent drawing
  • US20250330166A1 patent drawing

AI summary

Gate driver circuit, for a half bridge of a converter where a first switching device and a second switching device are controlled independently and in a complementary way comprising a first gate current mirroring circuit on a sink branch of a first gate driver buffer and a second gate current mirroring circuit on a sink branch of a second gate driver buffer to provide, in advance from pulse signals issued from the controller, a first early gate pullup command signal issuing from the first gate current mirroring circuit, for the second gate driver buffer under a turning off of a first switching device and a second early gate pullup command signal issuing from the second gate current mirroring circuit, for the first gate driver buffer from a turning off of a second switching device, in advance from gate pull up pulse signals issued from the controller.