Half-Bridge Gate Driver With Capacitive Level Shifting Stability
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Solution Overview
Problem
Existing gate driver circuits for high slew rate applications face challenges in achieving low latency and high efficiency due to parasitic inductances and supply voltage oscillations, leading to potential damage and spurious turn-on/off of power devices, while existing solutions like capacitive drivers are sensitive to supply oscillations and increase costs.
Innovation Solution
A gate driver circuit incorporating a differential capacitive level shifter and set-reset latches with feedback loops and hysteresis circuits to stabilize logic state changes, reducing sensitivity to supply oscillations and enhancing efficiency by using capacitive level shifting and hysteresis to manage current flows effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high slew rate signals are used to achieve high frequency and lower commutation losses, then efficiency and performance are improved, but parasitic inductances cause supply voltage oscillations that can damage power devices and cause spurious turn-on/off
Solution Approach 1:
A low-pass filter is introduced as an intermediary component between the power supply and the power devices. This filter mediates the harmful effect of supply voltage oscillations caused by high slew rate signals, allowing high frequency operation while protecting against voltage spikes that could damage devices or cause spurious switching
Solution Approach 2:
The parasitic inductances that cause harmful voltage oscillations are addressed by designing a low-pass filter that uses controlled impedance paths. The filter converts the potentially harmful high-frequency noise into beneficial filtered signals, allowing the system to operate at high frequencies while eliminating the damaging effects of parasitic elements
2Loss of energy
If capacitive gate drivers are used to achieve fast level shifting, then commutation losses are reduced, but the circuit becomes sensitive to supply oscillations and costs increase
Solution Approach 1:
A low-pass filter is introduced as an intermediary between the capacitive gate driver and the power supply. This filter protects the capacitive driver from supply oscillations while maintaining its fast commutation capabilities, eliminating the sensitivity issue without sacrificing performance
Solution Approach 2:
The gate driver circuit incorporates feedback mechanisms that monitor supply voltage conditions and adjust operation accordingly. This feedback system allows the capacitive driver to maintain fast commutation while automatically compensating for supply oscillations, reducing sensitivity without additional cost
3Power
If high voltage levels are used to drive the output transistors, then power delivery capability is improved, but latency from low voltage input to high voltage output increases
Solution Approach 1:
The gate driver circuit performs preliminary voltage level conversion and signal preparation in advance. By using a capacitive level shifter that pre-charges and prepares the high voltage signal before the actual switching event, the circuit reduces the time required for voltage transition while maintaining high power delivery capability
Solution Approach 2:
The circuit replaces traditional multi-stage voltage conversion mechanisms with a direct capacitive coupling approach. This substitution eliminates intermediate conversion steps and reduces the number of components involved in voltage level translation, thereby minimizing latency while maintaining high voltage output capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit achieves fast and efficient level shifting with low power consumption, reduces spurious logic state changes, and maintains high efficiency by stabilizing current flows and logic transitions, thus addressing the limitations of prior art.
Implementation Method 1
a capacitive level shifter circuit receiving said input signals at a low voltage level and shifting said input signals at a low voltage level to a high voltage level
Implementation Method 2
set-reset latches with feedback loops and hysteresis circuits to stabilize logic state changes
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
Gate driver circuit for a half bridge or full bridge output driver stage, identifying a high side branch connected to one or more high side transistors (Mp) and a low side branch connected to one or more low side transistors (Mn), comprising a high side gate driver (10; 21p) and a low side gate driver (10n; 21n) receiving input signals at a low voltage level (VDD) and operating with a high voltage level (VPP), outputting signals at a high voltage level as gate driving signals (Gp, Gn) for the high side transistors (Mp) and low side transistors (Mn) In the solution described the high side and the low side branches of the gate driver (11) include each a set-reset latch (24p, 24n) which signal output (Qp, Qpn) is fed as gate signal to the corresponding transistor (Mp, Mn) of the half bridge or full bridge driver (11), a differential capacitive level shifter circuit (23p, 23n) receiving said input signals at a low voltage level and outputting high voltage signals to drive the set (S) and reset (R) inputs of the set-reset latch (24p, 24n).