Half-Bridge Power Module Layout for Gate Oscillation Reduction
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Solution Overview
Problem
Current sharing mismatch between parallel-connected transistors in power semiconductor device modules leads to gate signal oscillation and reduced electrical efficiency due to differences in electrical impedances and conduction paths.
Innovation Solution
Implementing a half-bridge circuit power module with symmetric current conduction paths by using separate conductive clips to couple each transistor with patterned metal layers, and balanced connections to DC+ and DC− terminals, reducing impedance differences and improving path symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel-connected transistors are used in power modules, then current sharing imbalance occurs due to impedance differences, but using identical transistors and symmetric routing should reduce this imbalance
Solution Approach 1:
The patent applies asymmetry by intentionally introducing different lengths of dummy metal traces connected to the DC- terminal for each transistor. These asymmetric trace lengths create different parasitic inductances that compensate for the inherent impedance differences between parallel-connected transistors, thereby balancing current sharing and reducing gate signal oscillation.
2Reliability
If symmetric current conduction paths are implemented, then impedance differences are reduced, but device complexity increases due to additional metal layers and conductive elements
Solution Approach 1:
The patent resolves the complexity issue by utilizing the vertical dimension of the PCB substrate, adding metal traces on the opposite side of the substrate. This approach creates symmetric current conduction paths without significantly increasing lateral space requirements, as the symmetry is achieved through three-dimensional routing rather than expanding the planar footprint.
Data Source
AI summary
In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC− terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.