Half-Bridge Power Module Layout for Low-Stray Parallel Switching
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Solution Overview
Problem
Semiconductor power modules face challenges in achieving simultaneous switching and balanced operation of multiple semiconductor switches in parallel while minimizing stray inductances and maintaining a compact layout, which is crucial for high power density and efficiency, especially in applications like automotive power conversion where space is limited.
Innovation Solution
A power module design featuring a substrate with elongated inner and outer load tracks, where semiconductor switches are mounted on the outer and intermediate tracks and electrically connected, allowing for symmetric operation and reduced stray inductances, utilizing a DBC substrate with copper layers and insulating ceramic, and incorporating wirebonds or other connections for efficient current handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor switches are operated in parallel to achieve high output powers, then the total current capacity increases, but the module size increases and space is consumed
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional stacked architecture where semiconductor switches are arranged in multiple layers vertically. This dimensional change allows multiple switches to be integrated in parallel without increasing the horizontal footprint, thereby maintaining high output power while minimizing module size.
Solution Approach 2:
The patent implements a nested structure where semiconductor switches, substrates, and interconnection layers are stacked and integrated within each other vertically. Each layer is positioned above the previous one, creating a compact nested arrangement that maximizes current capacity within a minimal space envelope.
2Quantity of substance
If multiple semiconductor switches are mounted in parallel to achieve high output powers, then the current capacity increases, but the layout size increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange multiple semiconductor switches in parallel along the third dimension (height) rather than spreading them out in the horizontal plane. This allows the layout to maintain a compact footprint while accommodating multiple switches for high current capacity.
Solution Approach 2:
The patent merges multiple semiconductor switches and their supporting substrates into a single integrated stacked structure. The substrates are bonded together with interconnection layers in between, creating a unified compact assembly that provides high current capacity without proportionally increasing layout area.
3Productivity
If conventional substrate layouts are used with multiple semiconductor switches, then parallel operation is achieved, but stray inductances increase
Solution Approach 1:
The patent reduces stray inductances by transitioning to a vertical stacked architecture where current paths are shortened and optimized in three dimensions. The interconnection layers are positioned strategically between substrates to minimize loop areas and parasitic inductances, achieving low stray inductance while maintaining parallel operation of multiple switches.
Solution Approach 2:
The patent optimizes the local electrical properties of interconnection layers and substrate configurations to minimize stray inductances. Each interconnection layer is designed with specific trace patterns and positioning that locally reduce parasitic effects, and the overall stacked structure creates optimized current pathways that minimize total stray inductance.
Data Source
AI summary
A half bridge power module (1) comprising a substrate (2) comprising an inner load track (11), two intermediate load tracks (12, 14) and two outer load tracks (10,13), wherein an external terminal is mounted on one of the intermediate load tracks (12, 14), an external terminal (3, 4) is mounted on one of the outer load tracks (10, 13) and an external terminal (5) is mounted on the inner load track (11); wherein semiconductor switches (101, 12, 105, 106) are mounted on the outer load tracks (10, 13) and are electrically connected to the intermediate load track (12); and semiconductor switches (103, 104, 107, 108) are mounted on the intermediate load tracks (12, 14) and are electrically connected to the inner load track (11).