Half-Bridge Transistor Package Layout for Low Inductance and Heat Spreading
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Solution Overview
Problem
Existing package designs for automotive applications face challenges in achieving high electrical performance and thermal reliability due to limitations in die pad size, thermal spreading, and freedom of chip placement, leading to increased conductive losses and restricted thermal performance.
Innovation Solution
A package design featuring two transistor chips connected in a half-bridge configuration on a single integral electrically conductive body, with one chip in a drain-down arrangement and the other in a source-down arrangement, allowing vertical current flow and a compact design with reduced inductive losses, enhanced thermal reliability, and increased customizability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single integral electrically conductive body is used to mount both transistor chips, then thermal reliability and electrical performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the die pad and the electrically conductive body into a single integral structure, eliminating the need for separate mounting components. This integration improves thermal reliability by providing direct thermal coupling between the transistor chips and the heat dissipation path, while the unified structure simplifies manufacturing by reducing assembly steps and potential failure points from separate component bonding.
Solution Approach 2:
The single integral electrically conductive body serves multiple functions simultaneously: it acts as the die pad for mounting both transistor chips, provides electrical connection paths for all terminals, and functions as the primary heat dissipation structure. This multi-functionality improves reliability by ensuring consistent thermal and electrical performance while reducing the number of discrete components that would otherwise be required.
2Loss of energy
If one transistor chip is in drain-down arrangement and the other in source-down arrangement, then inductive losses are reduced and electrical performance is improved, but chip placement constraints increase
Solution Approach 1:
The patent employs asymmetric chip orientations where one transistor chip is mounted in drain-down arrangement and the other in source-down arrangement on the same die pad. This asymmetric configuration minimizes the commutation loop area between the two transistors, thereby reducing inductive losses and improving electrical performance. The single integral electrically conductive body provides the necessary asymmetric terminal arrangements to accommodate this configuration.
Solution Approach 2:
The invention utilizes the vertical dimension by allowing terminals to be formed on both main surfaces of the transistor chips. This enables the drain or collector terminal of one chip and the source or emitter terminal of the other chip to be positioned on opposite surfaces, creating a compact three-dimensional current path that reduces loop inductance while maintaining placement flexibility through the integral conductive body's multi-surface connectivity.
3Reliability
If a large die pad area is provided, then thermal spreading is enhanced and thermal reliability is improved, but package size increases
Solution Approach 1:
The single integral electrically conductive body simultaneously serves as a large-area die pad for optimal thermal spreading and as the compact mounting structure for both transistor chips. The unified structure ensures that the entire conductive body contributes to heat dissipation without requiring additional separate heat spreader components, thereby achieving enhanced thermal reliability within a space-efficient footprint.
Solution Approach 2:
By merging the die pad function and the heat dissipation structure into a single integral electrically conductive body, the patent maximizes the effective thermal spreading area without proportionally increasing package size. The integrated design ensures that the conductive body's full surface area is utilized for both electrical connections and thermal management, achieving optimal thermal performance in a compact configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved electrical performance and thermal reliability by minimizing inductive losses and maximizing chip placement flexibility, resulting in a package with enhanced thermal spreading and reduced conductive losses.
Implementation Method 1
a single integral electrically conductive body... enhanced thermal spreading
Implementation Method 2
single integral electrically conductive body... reduced inductive losses
Data Source
AI summary
A package includes a single integral electrically conductive body, a first chip with an integrated transistor and including a first terminal, a second terminal, and a third terminal, wherein the second terminal and the third terminal are formed on one main surface of the first chip and the first terminal is formed on an opposing main surface of the first chip, and a second chip with an integrated transistor and comprising a fourth, fifth and sixth terminals, wherein the fourth terminal and the sixth terminal are formed on one main surface of the second chip and the fifth terminal is formed on another surface of the second chip, wherein the first chip and the second chip are connected to form a half bridge.