Half-Bridge Converter PWM Phase Shift for Mode Transition Limits
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Solution Overview
Problem
Existing control methodologies for half-bridge converters face challenges in switching between complementary and non-complementary modes, risking violations of constraints such as dead-time and minimum pulse-width, which can limit the maximum voltage available across the load.
Innovation Solution
A processor device configures the control signals for the upper and lower switches of a half-bridge converter to switch between modes by determining a time-shift for the PWM signals, ensuring compliance with dead-time and minimum pulse-width constraints, and optionally setting the time-shift to zero if center-aligned PWM signals fulfill these constraints, thereby reducing processor workload and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control methodology is changed between complementary and non-complementary modes, then adaptability to different output current situations is improved, but risk of violating bridge converter and load constraints increases
Solution Approach 1:
The patent implements dynamic switching between complementary and non-complementary control modes based on real-time operating conditions. The processor device monitors the desired output current and automatically selects the appropriate control methodology, allowing the system to adapt to different situations while maintaining constraint compliance through controlled transition timing.
Solution Approach 2:
The patent applies preliminary action by introducing a time-shift parameter before actually switching between control modes. This time-shift prepares the control signals in advance to ensure that dead-time and minimum pulse-width constraints are satisfied during the transition, preventing constraint violations before they can occur.
2Reliability
If dead-time and minimum pulse-width constraints are enforced during mode switching, then reliability is improved, but maximum voltage available across load is reduced
Solution Approach 1:
The patent changes the timing parameter of control signals by introducing a time-shift that is dynamically adjusted based on the switching transition requirements. This parameter modification allows the system to maintain constraint compliance while minimizing the impact on voltage output, as the time-shift is optimized to be as small as possible while still ensuring reliable operation.
3Reliability
If processor continuously monitors and adjusts control signals to prevent constraint violations, then reliability is improved, but processor workload and power consumption increase
Solution Approach 1:
The patent implements self-service by designing the control system to automatically detect when mode switching is required and to self-correct timing issues through the time-shift mechanism. The processor only intervenes when necessary to calculate and apply the time-shift, rather than continuously monitoring and adjusting all parameters, thereby reducing computational workload and power consumption while maintaining reliability.
Data Source
Figure 1a~3b
Figure 3c~4
Figure 5a~6c
AI summary
A computer system comprising a processor device configured to switch between switching modes of a load (10) is presented. The switching modes are a complementary switching mode and a non-complementary switching mode of an upper switch (110) and a lower switch (120) of a first half-bridge converter (100) configured to provide a wanted power to a load (10). The processor device is configured to provide a first upper control signal (115) to the upper switch (110) and a first lower control signal (125) to the lower switch (120) as center aligned PWM-signals at a first PWM period. Responsive to determining that a current switching mode is to be changed at a second PWM period, the processor device is further configured to determine a time-shift for shifting the first upper control signal (115) and the first lower control signal (125), and to provide the first upper control signal (115) shifted by the time-shift to the upper switch (110) and the first lower control signal (125) shifted by the time-shift to the lower switch (120) at the second PWM period.