Half-Bridge PWM Output Stage With Adaptive Dead Time Control

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Solution Overview

Problem

Traditional dead time control in half bridge output stages is inflexible and unable to adapt to variations in process and supply voltage, leading to potential cross-conduction and damage from voltage shoot-through.

Innovation Solution

A PWM output stage with adaptive dead time control, comprising a half bridge output stage, a gate control circuit, a detection circuit, and control logic that adjusts delay times based on detected glitch events to prevent cross-conduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional simple logic gates are used for dead time control, then the circuit structure is simple, but the dead time cannot be adjusted and is affected by process and supply voltage variation

Engineering Contradiction:
Improvecircuit structureVSAvoiddead time adjustability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic dead time control by replacing static logic gates with a controllable delay circuit. The delay amount is dynamically adjusted based on process and supply voltage conditions, allowing the dead time to adapt to varying operating conditions while maintaining circuit functionality.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the delay parameter of the dead time control circuit based on detected process and supply voltage variations. By measuring actual operating conditions and adjusting the delay parameter accordingly, the system maintains optimal dead time across different process corners and voltage levels.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If fixed dead time is used, then the control circuit is simple, but cross-conduction may occur under process and voltage variation leading to voltage shoot-through

Engineering Contradiction:
Improvecontrol circuitVSAvoidprotection against cross-conduction
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the actual dead time is monitored and compared against required values. Based on this feedback, the control circuit adjusts the delay parameter to ensure sufficient dead time is maintained, preventing cross-conduction and voltage shoot-through under varying conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary adjustment of the dead time parameter based on detected process and voltage conditions before cross-conduction can occur. By proactively setting the appropriate delay value based on operating conditions, the system prevents harmful effects before they manifest.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If adaptive dead time control is implemented, then the reliability is improved, but the device complexity increases

Engineering Contradiction:
Improveprotection against cross-conductionVSAvoidcontrol circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-adjusting dead time control system that automatically detects process and voltage variations and adjusts its own delay parameter without external intervention. The circuit monitors its own operating conditions and makes real-time adjustments, reducing the need for external calibration while maintaining high reliability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10958259B2Pulse width modulation output stage with dead time control
Publication Date: 2021.03.23 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
  • US10958259B2 patent drawing
  • US10958259B2 patent drawing
  • US10958259B2 patent drawing

AI summary

A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.