Half-Bridge PWM Timing Shift for Safe Mode Switching

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Solution Overview

Problem

Existing bridge converter control methods face challenges in switching between complementary and non-complementary switching modes, risking violations of constraints such as dead-time and minimum pulse-width, which can limit the maximum voltage across the load.

Innovation Solution

A processor device is configured to switch between switching modes by determining a time-shift for control signals based on dead-time and minimum pulse-width constraints, ensuring compliance with these constraints and optimizing power delivery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If control methodology is changed between complementary and non-complementary switching modes, then adaptability to different operating conditions is improved, but risk of violating dead-time and minimum pulse-width constraints increases

Engineering Contradiction:
Improveadaptability to different operating conditionsVSAvoidrisk of constraint violation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by calculating and storing optimal time-shift values in advance for different operating conditions. When switching between complementary and non-complementary modes, the pre-calculated time-shift values are applied immediately, ensuring constraint compliance without real-time calculation delays or violations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the timing parameter of control signals by introducing a time-shift offset when switching between switching modes. This parameter adjustment ensures that dead-time and minimum pulse-width constraints are maintained during mode transitions, resolving the contradiction between adaptability and reliability.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If center aligned PWM signals are used without time-shift, then device complexity is reduced, but constraint compliance during mode switching cannot be ensured

Engineering Contradiction:
Improvecontrol signal generation complexityVSAvoidconstraint compliance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent calculates optimal time-shift values in advance and stores them for different operating conditions. This preliminary calculation approach maintains simple center-aligned PWM generation while ensuring constraint compliance through pre-determined timing adjustments.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a time-shift offset as an intermediary parameter between the simple center-aligned PWM generation and the complex constraint requirements. This intermediary element maintains the simplicity of center-aligned control while ensuring constraint compliance during mode transitions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If mode switching is performed without time-shift adjustment, then switching speed is improved, but constraint violations occur during mode transitions

Engineering Contradiction:
Improvemode switching speedVSAvoidconstraint compliance during transitions
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent pre-calculates optimal time-shift values for different operating conditions and switching scenarios. This allows immediate application of appropriate time-shifts during mode transitions, achieving both fast switching speed and constraint compliance without real-time calculation overhead.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12573941B2Bridge converter control
Publication Date: 2026.03.10 VOLVO TRUCK CORP
  • US12573941B2 patent drawing
  • US12573941B2 patent drawing
  • US12573941B2 patent drawing

AI summary

A computer system comprising a processor device configured to switch between switching modes of a load is presented. The switching modes are a complementary switching mode and a non-complementary switching mode of an upper switch and a lower switch of a first half-bridge converter configured to provide a wanted power to a load. The processor device is configured to provide a first upper control signal to the upper switch and a first lower control signal to the lower switch as center aligned PWM-signals at a first PWM period. Responsive to determining that a current switching mode is to be changed at a second PWM period, the processor device is further configured to determine a time-shift for shifting the first upper control signal and the first lower control signal, and to provide the first upper control signal shifted by the time-shift to the upper switch and the first lower control signal shifted by the time-shift to the lower switch at the second PWM period.