Half-Bridge Inverter Switching Timing for Parasitic Ringing Suppression
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Solution Overview
Problem
Parasitic resonance during switching transitions in inverter circuits limits switching speed, generates noise, and increases design complexity due to voltage oscillations and electromagnetic interference (EMI), particularly in high-power applications with wide bandgap semiconductors.
Innovation Solution
The inverter circuitry is configured with a half-bridge configuration where the switching transition duration is set to match the inverse of the resonant frequency, using a frequency-dependent input impedance to reduce overshoot and parasitic ringing, with a sensor circuit to determine the ringing frequency and adjust the switching transition duration accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If switching speed is increased in inverter circuits, then productivity is improved, but voltage oscillation and parasitic resonance occur causing harmful effects
Solution Approach 1:
The patent applies zero placement to convert the harmful parasitic resonance into a beneficial effect by strategically positioning zeros of the transfer function at the resonant frequencies of the parasitic LC circuits. This cancels out the voltage oscillations caused by parasitic resonance, enabling fast switching speeds without the harmful voltage ringing that would normally occur.
Solution Approach 2:
The patent modifies the switching transition duration parameter to match specific values that place zeros at the parasitic resonant frequencies. By changing the switching time constant and transition duration to satisfy specific mathematical relationships with the parasitic L and C values, the system eliminates voltage oscillations while maintaining fast switching performance.
2Object-affected harmful factors
If switching transition duration is extended to reduce voltage oscillation, then harmful factors are reduced, but switching speed decreases
Solution Approach 1:
The patent identifies specific parameter values for switching transition duration that simultaneously achieve both goals: the transition duration is set to satisfy the zero placement condition (related to parasitic L and C values) while maintaining sufficiently fast switching. This optimized parameter selection eliminates voltage oscillations without requiring excessively long transition times that would reduce switching speed.
Solution Approach 2:
By using zero placement to convert parasitic resonance into a beneficial cancellation effect, the patent removes the need to extend switching transition duration for oscillation suppression. The harmful parasitic elements are transformed into a design feature that enables fast switching without voltage ringing, resolving the trade-off between switching speed and voltage oscillation suppression.
3Device complexity
If conventional switching methods are used, then device complexity is low, but electromagnetic interference and noise are generated
Solution Approach 1:
The patent modifies the switching waveform parameters (transition duration and timing) to satisfy zero placement conditions that eliminate parasitic resonance. By changing these temporal parameters rather than adding physical components, the system reduces EMI and noise without increasing circuit complexity, maintaining a simple circuit topology while achieving cleaner switching transitions.
4Object-affected harmful factors
If parasitic resonance is suppressed by traditional methods, then harmful factors are reduced, but device complexity increases
Solution Approach 1:
The patent suppresses parasitic ringing by optimizing switching transition parameters rather than adding physical damping components. By adjusting the switching duration and timing to satisfy mathematical relationships with parasitic L and C values, the system eliminates ringing without adding snubber circuits, resistors, or other complexity-increasing components.
Solution Approach 2:
The patent replaces physical/passive damping mechanisms (such as snubber circuits or damping resistors) with a control-based approach using zero placement in the transfer function. This substitutes hardware complexity with parameter optimization, achieving parasitic resonance suppression through timing and duration control rather than additional circuit components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively mitigates parasitic ringing, enabling faster switching speeds while reducing noise and EMI, thereby simplifying design and improving performance in high-power applications.
Implementation Method 1
During the switching transient, the output capacitance can form a resonance with the parasitic inductance in the commutation loop
Implementation Method 2
The second MOSFET switch may be associated with a switching-transition network including a frequency-dependent input impedance zin(f)
Data Source
AI summary
An inverter circuit is provided to substantially mitigate parasitic ringing and to enable fast switching under high power conditions.