Half-Bridge Power Switch Driver with Mirrored Signal Interlock

The patent applies parameter changes by dynamically adjusting the dead time duration based on the actual switching states and timing of the power switches. Instead of using a fixed conservative dead time, the circuit monitors the real-time switching events and adjusts the interlock delay parameter accordingly, allowing for minimal delay when switching conditions permit and extended delay when cross-conduction risk exists. This resolves the contradiction by making the reliability parameter adaptive rather than static.

The patent implements feedback mechanisms that continuously monitor the switching states, gate signals, and current flow conditions in the half-bridge circuit. This feedback information is used to dynamically adjust the interlock delay timing, ensuring that the delay is only extended when actual cross-conduction risk is detected. The feedback system allows the circuit to maintain minimal interlock delay under normal conditions while automatically increasing protection when needed, thus resolving the contradiction between efficiency and reliability.

The patent applies dynamics by making the interlock delay duration variable rather than fixed. The delay timing is dynamically adjusted based on the switching frequency, load conditions, and real-time switch state transitions. At higher switching frequencies, the system optimizes the delay to be as minimal as possible while maintaining safety, and automatically extends the delay when conditions require additional protection. This dynamic adaptation allows the circuit to maintain high productivity at elevated switching frequencies without suffering from fixed delay limitations.