Half-Bridge Power Semiconductor Package With Low-Inductance Terminal Stack
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Solution Overview
Problem
Existing power semiconductor packages face limitations in switching speed due to parasitic power loop inductances, non-uniform switching losses, and thermal performance issues, which are exacerbated by reduced space for power terminals and creepage spacing constraints.
Innovation Solution
A power semiconductor package design featuring a half-bridge electrical circuit with parallel substrate assemblies and a power terminal assembly that includes high-side and low-side power terminals on a shared substrate, minimizing parasitic inductance and optimizing current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package size is reduced to increase power density, then power density is improved, but power terminal conductor cross section area shrinks resulting in higher power terminal resistance
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration with multiple substrate assemblies arranged vertically. The power terminal substrate is positioned between first and second substrate assemblies, creating multiple current paths and utilizing vertical space to maintain adequate conductor cross-section area while reducing the package footprint.
Solution Approach 2:
The power terminal functions are segmented across multiple substrates and assemblies. The power terminal substrate handles high-side drain, low-side source, and mid-point connections separately, distributing the current paths across different layers and reducing resistance by providing multiple parallel conduction paths.
2Quantity of substance
If package size is reduced to increase power density, then power density is improved, but creepage spacing between adjacent power terminals decreases constraining high voltage operation
Solution Approach 1:
The patent uses vertical stacking to separate high-voltage power terminals across different substrate layers. The power terminal substrate positioned between first and second substrate assemblies provides three-dimensional creepage paths, allowing adequate electrical isolation in the vertical dimension while maintaining compact horizontal footprint.
Solution Approach 2:
The power terminal substrate acts as an intermediary layer providing both electrical connection and creepage isolation. It mediates between the first and second substrate assemblies, establishing proper voltage grading and maintaining required creepage distances through its physical structure and material properties.
3Power
If parallel power semiconductor transistors are used to increase current capacity, then current handling capacity is improved, but mismatches in parasitic common source inductances cause imbalanced source-drain currents
Solution Approach 1:
The patent creates equipotential connections by providing low-inductance common source paths for all parallel transistors. The substrate assemblies are designed with symmetric trace routing and equal-length connections to ensure all transistor sources are at the same electrical potential, eliminating current imbalance caused by inductance mismatches.
Solution Approach 2:
The patent merges the source connections of all parallel transistors into a common low-inductance path on the substrate. By combining multiple source traces into a unified copper layer or bus structure with minimal inductance, the system achieves balanced current distribution across all parallel devices.
Data Source
AI summary
A power semiconductor package includes a first substrate assembly with a power semiconductor die defining a high-side power switch, a second substrate assembly arranged parallel to the first substrate assembly which has a power semiconductor die defining a low-side power switch, and a power terminal assembly. The power terminal assembly includes a power terminal substrate arranged between the first and the second substrate assembly, a high-side drain power terminal electrically connected to an electrical drain circuit of the high-side power switch, a low-side source power terminal electrically connected to an electrical source circuit of the low-side power switch, and a mid-point power terminal electrically connected to an electrical source circuit of the high-side power switch and to an electrical drain circuit of the low-side power switch. The high-side drain power terminal, the low-side source power terminal, and the mid-point power terminal are each arranged on the power terminal substrate.