Half-Cascode Low-Noise Amplifier for Deep-Submicron CMOS
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Solution Overview
Problem
In deep submicron CMOS technology, conventional low noise amplifiers face challenges in achieving sufficient gain and noise performance due to lower supply voltages and increased input capacitance, which limits their effectiveness in wireless receivers.
Innovation Solution
The implementation of a half cascode low noise amplifier circuit configuration, where only one of the PMOS or NMOS transistors is cascoded with another transistor of the same type, optimized for operation at lower supply voltages, reduces the Miller effect and increases high-frequency gain while maintaining linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional low noise amplifier configuration is used in deep submicron CMOS technology, then the amplifier can be implemented with standard circuit topology, but the gain and noise performance are insufficient due to lower supply voltages and increased input capacitance
Solution Approach 1:
The amplifier is divided into two asymmetric cascode branches: one with a cascoded transistor configuration and the other without. This segmentation allows each branch to contribute differently to the overall performance, achieving improved noise figure and gain while maintaining adequate voltage headroom in deep submicron CMOS technology
Solution Approach 2:
The patent employs asymmetric cascode configuration where only one of the NMOS or PMOS transistors is cascoded, rather than using symmetric full cascode in both branches. This asymmetry optimizes the trade-off between noise performance, gain, and voltage headroom constraints in deep submicron technology
2Speed
If full cascode configuration is used, then high-frequency gain is increased, but supply voltage headroom is reduced which is problematic in deep submicron technology
Solution Approach 1:
Instead of applying full cascode configuration to both NMOS and PMOS branches, the patent applies cascode structure partially to only one branch. This partial action provides sufficient high-frequency gain improvement while conserving supply voltage headroom for other circuit requirements in deep submicron technology
3Reliability
If transistor cascoding is applied to both PMOS and NMOS, then noise performance is improved, but input capacitance increases which limits effectiveness
Solution Approach 1:
The patent extracts the cascode structure from one of the branches (either NMOS or PMOS) while retaining it in the other branch. This selective removal reduces the total input capacitance compared to full cascode in both branches, while still achieving improved noise performance through the remaining cascoded branch
Data Source
AI summary
Apparatus and methods are disclosed, such as those involving a low noise amplifier. One such apparatus includes a low noise amplifier circuit configured to receive a signal at an input node and to output an amplified signal at an output node. The low noise amplifier circuit includes a first transistor of a first polarity; and a second transistor of a second polarity complementary to the first polarity. The first and second transistors are connected in series between first and second supply voltage nodes via the output node. The circuit further includes a third transistor cascoded with one of the first transistor or the second transistor, but does not include a transistor cascoded with the other transistor. This configuration allows the low noise amplifier circuit to provide an increased high-frequency gain and linearity while having improved high-frequency system noise figure in, for example, deep submicron CMOS technology.