Half-Duplex SerDes PHY Circuit With Shared RX/TX Clocking

Solution Overview

Problem

Conventional Serializer/Deserializer (SerDes) physical layer circuits require duplicate circuits for receiving and transmitting, leading to large circuit area and high costs, which hinders miniaturization and cost-effectiveness.

Innovation Solution

A SerDes physical layer circuit design that shares circuits for both receive and transmit modes, utilizing a clock multiplication unit, sampling circuit, phase detector, multiplexer, parallel-to-serial converter, and transmission driver, where the voltage-controlled oscillator outputs different clocks for receive and transmit modes, and the multiplexer controls the coupling of phase detectors and charge pumps accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If duplicate circuits are used for receive and transmit functions, then both functions can be achieved independently, but circuit area becomes large

Engineering Contradiction:

Improveindependent receive and transmit functionsVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the receive and transmit circuits by sharing common components including voltage-controlled oscillator, charge pump, low pass filter, phase frequency detector, and parallel-to-serial converter. The multiplexer dynamically connects these shared components to either the data sampler (receive mode) or the parallel-to-serial converter (transmit mode), thereby achieving both functions with a single integrated circuit structure that occupies minimal area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared circuit components are designed to perform multiple functions. The voltage-controlled oscillator generates clocks for both data sampling in receive mode and parallel-to-serial conversion in transmit mode. The charge pump and low pass filter serve both the data sampler and parallel-to-serial converter. The multiplexer enables these universal components to be dynamically allocated to different functional paths based on operational mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If duplicate circuits are used for receive and transmit functions, then both functions can be achieved independently, but manufacturing cost increases

Engineering Contradiction:

Improveindependent receive and transmit functionsVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the receive and transmit circuits by sharing common components including voltage-controlled oscillator, charge pump, low pass filter, phase frequency detector, and parallel-to-serial converter. The multiplexer dynamically connects these shared components to either the data sampler (receive mode) or the parallel-to-serial converter (transmit mode), thereby achieving both functions with a single integrated circuit structure that occupies minimal area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared circuit components are designed to perform multiple functions. The voltage-controlled oscillator generates clocks for both data sampling in receive mode and parallel-to-serial conversion in transmit mode. The charge pump and low pass filter serve both the data sampler and parallel-to-serial converter. The multiplexer enables these universal components to be dynamically allocated to different functional paths based on operational mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If separate receive and transmit circuits are used, then signal receiving and transmission can be carried out independently, but device complexity increases

Engineering Contradiction:

Improveindependent signal receiving and transmissionVSAvoidcircuit structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent employs a multiplexer that dynamically reconfigures the circuit connections based on operational mode. In receive mode, the multiplexer connects the voltage-controlled oscillator to the data sampler and the phase detector to the charge pump. In transmit mode, it connects the voltage-controlled oscillator to the parallel-to-serial converter and the phase frequency detector to the charge pump. This dynamic switching capability allows a single circuit structure to adapt to different functional requirements without permanent dedicated pathways.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10536166B2Serializer/deserializer physical layer circuit

Publication Date: 2020.01.14 REALTEK SEMICON CORP

AI summary

Disclosed is a Serializer/Deserializer physical layer circuit (SerDes PHY) for receiving and transmitting data in a half-duplex manner, the SerDes PHY including: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a low pass filter, a voltage-controlled oscillator (VCO) and a loop divider; a sampling circuit sampling a received signal according to clocks from the VCO in a receive mode; a phase detector (PD) operating according to outputs of the sampling circuit; a multiplexer connecting the PD with the CP and disconnecting the PFD from the CP in the receive mode, and connecting the PFD with the CP and disconnecting the PD from the CP in a transmission mode; a parallel-to-serial converter converting parallel data into serial data according a clock from the VCO in the transmission mode; and a transmission driver outputting a transmission signal according to the serial data in the transmission mode.