3D Half-Flash Structure With Short Control Gate for Faster Programming
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Solution Overview
Problem
Conventional flash memory cells with lower coupling ratios experience slower programming and erasing times due to the resistance associated with the polysilicon control gate electrode, limiting their performance.
Innovation Solution
The introduction of a shorter control gate electrode and additional electrical contacts to the gate dielectric layer for programming and erasing, eliminating the resistance associated with the polysilicon control gate electrode, thereby increasing the coupling ratio and enhancing programming and erasing speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional flash memory cell structure with polysilicon control gate electrode is used, then the device structure is simple and easy to manufacture, but the resistance associated with the polysilicon control gate electrode results in slower programming and erasing times
Solution Approach 1:
The control gate is segmented into two parts: a polysilicon control gate electrode and a separate electrical contact to the gate dielectric layer. This segmentation allows the programming and erasing operation to use the gate dielectric contact directly, bypassing the polysilicon electrode resistance, while the polysilicon electrode can still serve other functions or be optimized separately.
Solution Approach 2:
An intermediary electrical contact is introduced to the gate dielectric layer, which serves as a mediator for programming and erasing operations. This intermediary contact provides a low-resistance path for charge transfer to the floating gate, eliminating the bottleneck caused by the polysilicon control gate electrode resistance.
2Speed
If the control gate electrode length is reduced to increase coupling ratio, then the programming speed improves, but the control gate coverage and electrical connection area are reduced
Solution Approach 1:
The electrical contact to the gate dielectric layer is positioned in a different spatial dimension and location relative to the control gate electrode. This allows the control gate electrode to be shortened in one dimension to improve coupling ratio, while the electrical contact provides the necessary electrical connection through a different spatial path, maintaining functionality without requiring large electrode area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in faster programming and erasing times for flash memory devices by increasing the coupling ratio, utilizing the electrical contact to the gate dielectric layer instead of the control gate electrode, thus avoiding resistance-related delays.
Implementation Method 1
a first tunnel dielectric layer formed over the substrate... charge accumulation in the floating gate
Implementation Method 2
charge accumulation in the floating gate... capacitance between the control gate and the floating gate (CONO)
Implementation Method 3
a voltage may be applied to the control gate resulting in charge accumulation in the floating gate
Data Source
AI summary
A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.